DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/28/2024 is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US. Pub. No. 2023/0012157, hereinafter “Yu”).
As to claims 14 and 1, (Original) Yu discloses a packaging structure [figures 15-18, a packaging structure], associated with its manufacturing method of the packaging structure, comprising:
a photonic integrated structure [abstract, forming a first photonic die, figures 15-18, photonic integrated structure 34] comprising:
one or more first openings [figures 15-18, one or more first openings of dielectric layer 36 to form pads], and
a conductive material [paragraph 41, The formation process may include etching-through dielectric layers 58 and dielectric layer 20B to form via openings, and to reveal vias 30, filling the via openings with conductive materials (such as TiN, TaN, Ti, Ta, Cu, W, Co, or the like), and performing a planarization process] disposed in each of the one or more first openings;
a first substrate [figures 15-18, first substrate 134] comprising:
one or more second openings [figures 15-18, one or more openings of top dielectric layer 142 of 134], and
a conductive material disposed in each of the one or more second openings [figures 15-18, conductive material disposed in each of the one or more second openings to form bond pads 140, paragraph 41, filling the via openings with conductive materials (such as TiN, TaN, Ti, Ta, Cu, W, Co, or the like), and performing a planarization process],
wherein each of the first openings is aligned with a corresponding one of the second openings [figures 15-18, each of the first openings is aligned with a corresponding one of the second openings 140], and the conductive material in the first opening is electrically connected with the conductive material in the corresponding second opening [figures 15-18, electric current path shown as the arrow passes through the second opening to the first opening, paragraph 44, the bond pads 140 in photonic wafer 164 being bonded to bond pads 62 in photonic wafer 64].
As to claims 15 and 2, (Original) Yu discloses the packaging structure of claim 14, associated with its manufacturing method of the packaging structure, wherein the photonic integrated structure comprises a first dielectric layer, and the one or more first openings pass through the first dielectric layer [figures 15-18, a first dielectric layer 36, the one or more first openings pass through 36].
As to claim 3, (Original) Yu discloses the manufacturing method of the packaging structure of claim 2, wherein the one or more second openings pass through the first substrate [figure 18, second openings pass through 134].
As to claim 4, (Original) Yu discloses the manufacturing method of the packaging structure of claim 2, wherein:
the first substrate has a first side and a second side opposite to the first side [figure 18, 134 has a top and a bottom side], and
the manufacturing method further comprises: thinning the first substrate from the second side of the first substrate, so that the one or more second openings pass through the first substrate [paragraph 35, bulk substrate 20A may be removed. The respective process is illustrated as process 216 in the process flow 200 as shown in FIG. 47. The resulting structure is shown in FIG. 9. Bulk substrate 20A may be removed using a planarization process (e.g., a CMP or grinding process), an etching process, a combination thereof, or the like. In accordance with some embodiments, dielectric layer 20B is also thinned. Dielectric layer 20B may be thinned as part of the removal process for bulk substrate 20A, or dielectric layer 20B may be thinned in a separate step].
As to claim 5, (Original) Yu discloses the manufacturing method of the packaging structure of claim 3, wherein the providing of the photonic integrated structure comprises:
forming the photonic integrated structure based on a Silicon-On-Insulator (SOI) substrate, wherein the SOI substrate includes a back substrate, an insulating layer, and a top
silicon layer, and the first dielectric layer is formed from the insulating layer in the SOI substrate [paragraph 35, bulk substrate 20A may be removed. The respective process is illustrated as process 216 in the process flow 200 as shown in FIG. 47. The resulting structure is shown in FIG. 9. Bulk substrate 20A may be removed using a planarization process (e.g., a CMP or grinding process), an etching process, a combination thereof, or the like. In accordance with some embodiments, dielectric layer 20B is also thinned. Dielectric layer 20B may be thinned as part of the removal process for bulk substrate 20A, or dielectric layer 20B may be thinned in a separate step];
removing the back substrate [paragraph 35, bulk substrate 20A may be removed. The respective process is illustrated as process 216 in the process flow 200 as shown in FIG. 47. The resulting structure is shown in FIG. 9. Bulk substrate 20A may be removed using a planarization process (e.g., a CMP or grinding process), an etching process, a combination thereof, or the like. In accordance with some embodiments, dielectric layer 20B is also thinned. Dielectric layer 20B may be thinned as part of the removal process for bulk substrate 20A, or dielectric layer 20B may be thinned in a separate step]; and
forming the one or more first openings in the first dielectric layer [paragraph 35, bulk substrate 20A may be removed. The respective process is illustrated as process 216 in the process flow 200 as shown in FIG. 47. The resulting structure is shown in FIG. 9. Bulk substrate 20A may be removed using a planarization process (e.g., a CMP or grinding process), an etching process, a combination thereof, or the like. In accordance with some embodiments, dielectric layer 20B is also thinned. Dielectric layer 20B may be thinned as part of the removal process for bulk substrate 20A, or dielectric layer 20B may be thinned in a separate step].
As to claim 6, (Currently Amended) Yu discloses the manufacturing method of the packaging structure of claim 5, wherein the forming of the one or more first openings in the first dielectric layer comprises: forming the one or more first openings removed. The respective process is illustrated as process 216 in the process flow 200 as shown in FIG. 47. The resulting structure is shown in FIG. 9. Bulk substrate 20A may be removed using a planarization process (e.g., a CMP or grinding process), an etching process, a combination thereof, or the like. In accordance with some embodiments, dielectric layer 20B is also thinned. Dielectric layer 20B may be thinned as part of the removal process for bulk substrate 20A, or dielectric layer 20B may be thinned in a separate step].
As to claim 7, (Currently Amended) Yu discloses the manufacturing method of the packaging structure of claim 5, wherein the forming of the one or more first openings in the first dielectric layer comprises: forming the one or more first openings
As to claim 8, (Currently Amended) Yu discloses the manufacturing method of the packaging structure of claim 4
As to claim 11, (Original) Yu discloses the manufacturing method of the packaging structure of claim 10, wherein the one or more photonic devices comprise at least one of a waveguide [abstract, a first photonic die, which includes forming a first silicon waveguide, and forming a first nitride waveguide], a grating coupler, an optical modulator, a directional coupler, a multi-mode interferometer, a photodetector, and an optical beam splitter.
As to claim 12, (Original) Yu discloses the manufacturing method of the packaging structure of claim 11, wherein a second dielectric layer is formed on the first side of the first dielectric layer, the second dielectric layer covers the one or more photonic devices, and the one or more first openings pass through the second dielectric layer [figure 18, second dielectric layer 36 formed on the first side of first dielectric layer, covers photonic devices and first opening].
As to claim 13, (Original) Yu discloses the manufacturing method of the packaging structure of claim 8, wherein a plurality of the first openings are aligned with a corresponding one of the one or more second openings [figure 18, a plurality of first openings are aligned with a corresponding to second openings].
As to claim 16, (Original) Yu discloses the packaging structure of claim 15, wherein the photonic integrated structure has a first side and a second side opposite to the first side [figures 15-18, the top side and the bottom side of 34], the first dielectric layer is located on the second side of the photonic integrated structure, and the second side of the photonic integrated structure faces toward the first substrate [figures 15-18, 36 is located on the bottom side of 34 facing toward 134].
As to claim 17, (Original) Yu discloses the packaging structure of claim 16, wherein the one or more second openings pass through the first substrate [figures 15-18, second openings pass through 134].
As to claims 18 and 9, (Currently Amended) Yu discloses the packaging structure of claim 17, associated with its manufacturing method of the packaging structure, comprising an additional dielectric layer [figures 15-18, an additional dielectric layer 58 located between 134 and 34] located between the photonic integrated structure and the first substrate,
the additional dielectric layer comprises one or more third openings and a conductive material disposed in each of the one or more third openings [figures 15-18, additional dielectric layer comprises third openings 60 and conductive material disposed in each of third openings],
the one or more third openings pass through the additional dielectric layer [figures 15-18, third openings 60 pass through additional dielectric layer 58], and
each of the one or more third openings is aligned with a corresponding one of the second openings, so that the conductive material in the third opening is electrically connected to the conductive material in the corresponding second opening [figures 15-18, each of the one or more third openings 60 is aligned with a corresponding one of second opening of 134, so that the conductive material in the third opening 60 is electrically connected to the conductive material in second opening].
As to claims 19 and 10, (Currently Amended) Yu discloses the packaging structure of any one of claim 17, associated with its manufacturing method of the packaging structure, wherein the first dielectric layer has a first side and a second side opposite to the first side [figure 18, 36 has a top side and a bottom side], the photonic integrated structure comprises one or more photonic devices disposed on the first side of the first dielectric layer [figure 18, one or more photonic devices 44 disposed on the top side of 36], and the second side of the first dielectric layer is bonded to the first substrate [figure 18, the bottom side of 36 is bonded to 134].
As to claim 20, (Original) see the above discussion of claim 14.
As to claim 21, (Original) see the above discussion of claim 15.
As to claim 22, (Original) see the above discussion of claim 16.
As to claim 23, (Original) see the above discussion of claim 17.
As to claim 24, (Original) see the above discussion of claim 5.
As to claim 25, (Currently Amended) see the above discussion of claim 18.
As to claim 26, (Currently Amended) see the above discussion of claims 10 and 19.
As to claim 27, (Original) see the above discussion of claim 11.
As to claim 28, (Original) see the above discussion of claim 12.
As to claim 29, (Original) see the above discussion of claim 13.
As to claim 30, (Original) Yu discloses the photonic integrated circuit chip of claim 23, wherein the photonic integrated circuit chip has a first surface and a second surface opposite to the first surface, and the photonic integrated circuit chip comprises one or more conductive paths extending between the first surface and the second surface of the photonic integrated circuit chip [figure 18, a first surface and a second surface opposite to the first surface, one conductive path 71 extending between the first surface and the second surface],
wherein the one or more first openings provided with conductive material are one or more first conductive openings, and the one or more second openings provided with conductive material are one or more second conductive openings [figure 18, conductive material provided in the openings through the layers], and
the one or more conductive paths each pass through one or more of the one or more first conductive openings and one or more of the one or more second conductive openings in sequence along a direction along which the conductive path extends from the first surface to the second surface [figure 18, conductive path 71 pass through one or more of the one or more first conductive openings and one or more of the one or more second conductive openings in sequence along a direction along which the conductive path extends from the first surface to the second surface, paragraph 50, arrow 71 is drawn to represent one of the electrical conductive paths, which includes through-vias 60 and 160 and the corresponding bonding pads, and the redistribution lines in redistribution structures 34 and 134].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al. (US. Pub. No. 2021/0302654) is considered as pertinent art as seen in figure 1 relating to claims 1, 14 and 20.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAN-YING YANG whose telephone number is (571)272-2211. The examiner can normally be reached Monday-Friday, 8am-5pm, EST.
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/NAN-YING YANG/ Primary Examiner, Art Unit 2629
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