DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “third conductor” of claims 1-3, 7, 12, and 15 must be shown or the feature(s) canceled from the claim(s). The drawings show that the metal oxide 230 is connected to conductor 233 which corresponds to the claimed first conductor, conductor 231 which corresponds to the claimed second conductor and conductor 242 which corresponds to the fourth conductor because it is composed of a first layer 242b and a second layer 242a as recited by the claims. There is no conductor in the drawings that corresponds to the claimed third conductor that is connected to the metal oxide and in contact with the first conductor as recited by at least claim 1. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US 20150349132 A1) in view of Isobe et al. (US 20130221347 A1) herein after “Isobe”.
Regarding claim 1, Figs. 1B and 9 of Yamazaki disclose a semiconductor device (Fig. 9, semiconductor device, ¶ [0215]) comprising:
a first conductor (see Annotation 1, Fig. 9 of Yamazaki, C1);
a second conductor (see Annotation 1, Fig. 9 of Yamazaki, C2);
a first insulator (Fig. 9, insulator 490, ¶ [0224]);
a first transistor (Fig. 9, transistor 2100, ¶ [0215]) over the first insulator (490); and
a second insulator (Fig. 9, insulator 494, ¶ [0224]) over the first transistor (2100),
wherein the first transistor (2100) comprises a first metal oxide (Fig. 1B, “semiconductor 406b is an oxide semiconductor”, ¶ [0086]), a third conductor (Fig. 1B, conductor 416b, ¶ [0076]) electrically connected to the first metal oxide (406b), a fourth conductor (Fig. 1B, conductor 416a, ¶ [0076]) electrically connected to the first metal oxide (406b), a third insulator (Fig. 1B, insulator 412, ¶ [0076]) over the first metal oxide (406b), and a fifth conductor (Fig. 9, conductors 496b, ¶ [0231]) over the third insulator (412),
wherein the top surface of the fifth conductor (496b) is in contact with the second insulator (494),
wherein the first conductor (C1) comprises a portion inside a first opening of the first insulator (490), a region in contact with a side surface of the third conductor (416b), and a portion inside a second opening of the second insulator (494),
wherein the second conductor (C2) comprises a region in contact with the fourth conductor (416a) and a portion inside a third opening of the second insulator (494), and
wherein the top surface of the first conductor (C1) and the top surface of the second conductor (C2) are level or substantially level with each other.
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Annotation 1, Fig. 9 of Yamazaki
Yamazaki discloses that the fourth conductor “include regions functioning as a source electrode and a drain electrode of the transistor” (see Yamazaki, ¶ [0077]), but fails to disclose wherein the fourth conductor comprises a first layer and a second layer over the first layer.
In the similar field of endeavor of oxide semiconductor devices, Isobe discloses using “a stack of a tantalum nitride film and a tungsten film” as a source or drain electrode (see Isobe, ¶ [0136]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to substitute the source/drain electrode of Yamazaki for the stack of a tantalum nitride film and a tungsten film as disclosed by Isobe. The claimed stack structure was known in the prior art and one skilled in the art could have combined the structure of Isobe with that of Yamazaki as claimed with no change in their respective functions, and the combination would have yielded the predictable result of creating a source/drain electrode. See KSR International Co. V. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 5, Yamazaki and Isobe disclose the semiconductor device according to claim 1 as applied above, but Yamazaki fails to disclose wherein the first layer comprises tantalum nitride, and
wherein the second layer comprises tungsten.
In the similar field of endeavor of oxide semiconductor devices, Isobe discloses wherein the first layer comprises tantalum nitride, and
wherein the second layer comprises tungsten (“a stack of a tantalum nitride film and a tungsten film”, ¶ [0136]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to substitute the source/drain electrode of Yamazaki for the stack of a tantalum nitride film and a tungsten film as disclosed by Isobe. The claimed stack structure was known in the prior art and one skilled in the art could have combined the structure of Isobe with that of Yamazaki as claimed with no change in their respective functions, and the combination would have yielded the predictable result of creating a source/drain electrode. See KSR International Co. V. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 6, Yamazaki and Isobe disclose the semiconductor device according to claim 1 as applied above, but Yamazaki and Isobe fail to explicitly disclose wherein a thickness of the fourth conductor is greater than or equal to 10 nm and less than or equal to 50 nm, and
wherein a thickness of the first layer is greater than or equal to 2 nm and less than or equal to 10 nm.
However, it has been held that where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been an obvious matter of design choice to form the fourth conductor and first layer with the recited thicknesses, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding claim 7, Yamazaki and Isobe disclose the semiconductor device according to claim 1 as applied above, and Fig. 9 of Yamazaki further discloses wherein a width of the region of the first conductor (C1) that is in contact with the side surface of the third conductor (416b) is smaller than a width of the portion of the first conductor (C1) that is inside the second opening of the second insulator (494) in a cross-sectional view in a channel length direction.
Regarding claim 8, Yamazaki and Isobe disclose the semiconductor device according to claim 1 as applied above, and Fig. 1B of Yamazaki further discloses wherein the first metal oxide (406b) comprises one or more selected from indium, zinc, gallium, aluminum, and tin (“The semiconductor 406b is an oxide semiconductor containing indium, for example. The semiconductor 406b can have high carrier mobility (electron mobility) by containing indium, for example. The semiconductor 406b preferably contains an element M. The element M is preferably aluminum, gallium, yttrium, tin”, ¶ [0086]).
Allowable Subject Matter
Claims 2-4, 9-16 are allowed.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 2, Figs. 1B and 9 of Yamazaki disclose a semiconductor device comprising:
a first conductor (C1);
a second conductor (C2);
a first insulator (490);
a first transistor (2100),
a second transistor (Fig. 9, transistor 2200, ¶ [0215]), and
a second insulator (494) over the first transistor (2100) and the second transistor (2200),
wherein the first transistor (2100) comprises a first metal oxide (406b), a third conductor (416b) electrically connected to the first metal oxide (406b), a fourth conductor (416a) electrically connected to the first metal oxide (406b), a third insulator (412) over the first metal oxide (406b), and a fifth conductor (496b) over the third insulator (412),
wherein the first conductor (C1) comprises a portion inside a first opening of the first insulator (490), a region in contact with a side surface of the third conductor (416b), and a portion inside a second opening of the second insulator (494),
wherein the second conductor (C2) comprises a region in contact with the fourth conductor (416a) and a portion inside a third opening of the second insulator (494),
wherein the top surface of the first conductor (C1) and the top surface of the second conductor (C2) are level or substantially level with each other.
Yamazaki fails to disclose a third transistor over the first insulator;
the second insulator over the third transistor,
wherein the fourth conductor comprises a first layer and a second layer over the first layer,
wherein the second transistor comprises a second metal oxide, a sixth conductor electrically connected to the second metal oxide, a seventh conductor electrically connected to the second metal oxide, a fourth insulator over the second metal oxide, and an eighth conductor over the fourth insulator,
wherein the third transistor comprises the second metal oxide, the seventh conductor electrically connected to the second metal oxide, a ninth conductor electrically connected to the second metal oxide, a fifth insulator over the second metal oxide, and a tenth conductor over the fifth insulator.
The prior art made of record herein, as well as other pertinent prior art Yamazaki et al. (US 20200243514 A1), Okamoto et al. (WO 2020008304 A1), and Hodo et al. (US 20150372122 A1), alone or in combination fail to disclose or fairly suggest the limitations of claim 2 not disclosed by Yamazaki.
Claims 9-12 are allowed based on their dependence on claim 2.
Regarding claim 3, Figs. 1B and 13 of Yamazaki disclose a semiconductor device comprising:
a first conductor (C1);
a second conductor (C2);
a first insulator (490);
a first transistor (2100),
a second transistor (2200), and
a second insulator (494) over the first transistor (2100) and the second transistor (2200),
a capacitor (Fig. 13, capacitor 3400, ¶ [0243]),
wherein the first transistor (2100) comprises a first metal oxide (406b), a third conductor (416b) electrically connected to the first metal oxide (406b), a fourth conductor (416a) electrically connected to the first metal oxide (406b), a third insulator (412) over the first metal oxide (406b), and a fifth conductor (496b) over the third insulator (412),
wherein the first conductor (C1) comprises a portion inside a first opening of the first insulator (490), a region in contact with a side surface of the third conductor (416b), and a portion inside a second opening of the second insulator (494),
wherein the second conductor (C2) comprises a region in contact with the fourth conductor (416a) and a portion inside a third opening of the second insulator (494),
wherein the top surface of the first conductor (C1) and the top surface of the second conductor (C2) are level or substantially level with each other.
Yamazaki fails to disclose a third transistor over the first insulator;
the second insulator over the third transistor,
wherein the fourth conductor comprises a first layer and a second layer over the first layer,
wherein the second transistor comprises a second metal oxide, a sixth conductor electrically connected to the second metal oxide, a seventh conductor electrically connected to the second metal oxide, a fourth insulator over the second metal oxide, and an eighth conductor over the fourth insulator,
wherein the third transistor comprises the second metal oxide, the seventh conductor electrically connected to the second metal oxide, a ninth conductor electrically connected to the second metal oxide, a fifth insulator over the second metal oxide, and a tenth conductor over the fifth insulator,
wherein the second conductor and the eighth conductor are electrically connected to each other.
The prior art made of record herein alone or in combination fail to disclose or fairly suggest the limitations of claim 3 not disclosed by Yamazaki.
Claims 4, and 13-16 are allowed based on their dependence on claim 3.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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