Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1, 2, and 4-9 are pending and rejected. Claims 4 and 10 are withdrawn.
Election/Restrictions
Applicant’s election without traverse of group I, species C in the reply filed on 12/29/2025 is acknowledged.
Claims 3 and 10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species and invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/29/2026.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 413 (Fig. 4), 518, 558, (Fig. 5), 690 (Fig. 6). Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 6, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Papasouliotis, US 7,482,247 B1 (provided on the IDS of 1/17/2025).
Regarding claim 1, Papasouliotis teaches a method for processing substrates (conformal nanolaminate dielectric deposition and etch back processes for filling high aspect ratio gaps, abstract), the method comprising:
providing a substrate having a feature having a feature opening to a process chamber (performing deposition and etching in a chamber on a substrate having gaps, Col. 2, lines 27-43, Col. 4, lines 42-53, and Fig. 1A);
conformally depositing a first portion of a material into the feature (partially filling the gap with a conformal dielectric, Col. 5, lines 8-27 and Fig. 1B);
after partially depositing the first portion of the material, exposing the substrate to an etching species to etch an angular opening at or near the feature opening to form an etched surface (performing an etch back process by etching with plasma gases, Col. 8, lines 55-67 and Col. 10, lines 27-38 and Col. 11, lines 7-19, where the profile of the partially-filled gap following etching allows for void free gap fill with conformal dielectric deposition, where as in Fig. 1C, the opposing advancing faces of the conformally deposited film are no longer parallel such that the gap will fill without risk of a weak seam developing, Col. 12, lines 16-28 and Fig. 1C, where in Fig. 1C the etched opening is angular, indicating that is a desired etching profile); and
depositing a second portion of the material onto the etched surface to fill the feature (after etching, further filling of the partially filled gap is conducted, where etching and deposition is repeated until the gap is filled, Col. 2, lines 27-43).
They teach that after etching, the gap will fill without risk of a weak seam developing (Col. 12, lines 16-28). They depict performing the etching step before a seam forms in the feature (Fig. 1A-D). From this, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have stopped the deposition and performed the etching process prior to the formation of a void or seam because Papasouliotis teaches that after etching the gap will fill without risk of a seam forming, indicating that forming a seam is undesirable and because they depict performing the etching prior to seam or void formation such that it will be expected to facilitate the filling of the gap without formation of a void or seam.
Regarding claim 6, Papasouliotis suggests the process of claim 1. They teach that the etch and passivation steps can be carried out in situ or in a different chamber, for example in a cluster tool with different chambers without a vacuum break (Col. 4, lines 42-53).
Regarding claim 7, Papasouliotis suggests the process of claim 1. They further teach etching using plasma etch chemistries that include fluorine such as F2, HF, NF3, etc. (Col. 9, lines 27-39). They teach that oxygen may optionally be included and that an H2/He/NF3-based chemistry is preferred (Col. 9, lines 27-39). From this, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have selected an oxygen-free etching species such as an H2/He/NF3-based chemistry because Papasouliotis indicates that such an etchant gas is preferred, where oxygen is optional, indicating it is not required.
Claims 1 and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Singhal, US 2018/0005801 A1.
Regarding claim 1, Singhal teaches a method for processing substrates (methods for performing deposition and etch processes in an integrated tool, abstract), the method comprising:
providing a substrate having a feature having a feature opening to a process chamber (providing a wafer in a plasma processing chamber, where the wafer has one or more gaps, 0084 and Fig. 1A);
conformally depositing a first portion of a material into the feature (depositing a first dielectric layer in the one or more gaps via ALD, where the film is conformal, 0085 and Fig. 1A);
after partially depositing the first portion of the material, exposing the substrate to an etching species to etch an angular opening at or near the feature opening to form an etched surface (anisotropically etching the first dielectric layers with slope control to create a tapered positive slope in the as-deposited film of the first dielectric layer, where the etch can selectively remove more dielectric material near the top of the gap than inside and near the bottom of the gap, such that an angular opening will be provided, 0086 and Fig. 1B); and
depositing a second portion of the material onto the etched surface to fill the feature (depositing a second dielectric layer in the one or more gaps over the first dielectric layer via ALD in the plasma processing chamber to fill and close the one or more gaps, 0089 and Fig. 1C).
They teach that multi-step deposition process are used where etching may be done to remedy or prevent void formation in the gap (0004 and 0027). They teach that the gap may be free of voids (0030 and Fig. 1C). They depict performing the etching step before a seam forms in the feature (Fig. 1A-B). From this, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have stopped the deposition and performed the etching process prior to the formation of a void or seam because Singhal teaches that the multi-step deposition is used to prevent void formation and because they depict performing the etching prior to seam or void formation such that it will be expected to facilitate the filling of the gap without formation of a void or seam.
Regarding claim 5, Singhal suggests the process of claim 1. Singhal further teaches an apparatus for the process that includes a pedestal that can support a wafer (0034 and Fig. 2). Since there is no indication that multiple wafer are processed at the same time, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used a single-wafer process chamber as the process chamber because the chamber described by Singhal includes a pedestal for a wafer, suggesting it processes a single wafer and because there is no indication that multiple wafers are processed.
Regarding claim 6, Singhal suggests the process of claim 1. They further teach performing the multiple deposition-etch-deposition sequences in the same chamber (0077 and 0083). They teach that the pressure is between about 0.3 and about 1.0 Torr while performing deposition and etching steps (0010). From this, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have deposited the first portion and to have etched without breaking vacuum because they teach performing the processes in the same chamber, where the processes are done under a vacuum (low pressure) such that it will be expected to maintain the pressure in the desired range as opposed to requiring additional pump down processes.
Regarding claim 7, Singhal suggests the process of claim 1. They further teach etching using nitrogen trifluoride, where there is no indication that oxygen is included (0086), such that the etching species will be oxygen-free.
Regarding claim 8, Singhal suggests the process of claim 1. They further teach that the anisotropic etch can selectively remove more dielectric material near the top of the gap than inside and near the bottom of the gap (0086). They teach that “near the top of the gap” or “near the opening” is defined as an approximate position or an area within the gap corresponding to about 0-10% of the gap depth (0086). Therefore, since more material is removed “near the top of the gap” to provide the sloped edge, the angular opening will be etched in an area corresponding to about 0-10% of the gap depth so as to overlap the claimed range. According to MPEP 2144.05, “in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.”
Claims 2, 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Singhal as applied to claim 1 above, and further in view of Mays, US 2020/0365447 A1.
Regarding claims 2, 4, and 9, Singhal suggests the process of claim 1. They teach that the gap can be filled using any suitable deposition technique, such as ALD, CVD, PECVD, HDP-CVD, etc. (0030)
They do not teach depositing the second material by CVD and a post-treatment process.
Mays teaches depositing a solid dielectric liner on the inner surfaces of openings in a surface using a non-flowable process, and subsequently filling the remaining empty volume of the openings with a fill dielectric using a flowable process (abstract). They teach that the combination maximizes the individual strengths of the non-flowable and flowable processes due to the synergetic effect achieved by their combined use, while reducing their respective drawbacks (abstract). They teach that the method begins with providing a structure with one or more openings (0055, Fig. 3 and Fig. 4A). They teach that the openings are conformally coated with a solid dielectric material layer using methods such as ALD, PEALD, CVD, or PECVD (0064-0065, Fig. 3, and Fig. 4B). They teach that the solid dielectric liner may be grown for any suitable time and may include multiple deposition cycles of one or more non-flowable processes, as long as the dielectric liner does not close the openings (0067). They teach that once the openings are coated with the dielectric liner, the remaining open volume of the openings is filled with a dielectric material using one or more flowable processes (0068, Fig. 3, and Fig. 4C). They teach that filling the lined openings with the fill dielectric may include providing gaseous precursors using a flowable CVD process, where, first precursor are directed to the structure in a CVD chamber where they react to form a flowable fill dielectric which can fill the remaining volume of the openings, followed by applying an excitation to facilitate cross-linking of the compounds of the flowable fill dielectric into a solid matrix of the fill dielectric, now set in the openings (0069). They teach that applying excitation to crosslink the fluid precursor into the solid fill dielectric may include plasma treatment (0072). Since they teach depositing the fill material by a flowable CVD process, where they indicate that the precursors are provided by heating (0071), it is understood include a thermal CVD process, i.e., non-plasma.
From the teachings of Mays, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the process of Singhal to have deposited the first layer by a non-flowable process such as ALD or PEALD and then to have deposited the fill layer by a thermal (flowable) CVD process followed by a plasma treatment for solidification because Mays teaches that such a process is desirable for filling openings in features, while maximizing the individual strengths of the non-flowable and flowable processes due to the synergetic effect achieve by their combined use, while reducing their respective drawbacks, where PEALD is a suitable conformal film deposition as an alternative to ALD such that it will be expected to provide the conformal film deposition and subsequent fill process as desired. Therefore, the first portion of the material is deposited using PEALD and the second portion of the material is deposited using thermal CVD with a plasma post-treatment process.
Claims 1, 5, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Babich, US 2012/0217590 A1.
Regarding claim 1, Babich teaches a method for processing substrates (a method for filling openings in a substrate, abstract), the method comprising:
providing a substrate having a feature having a feature opening to a process chamber (positioning a semiconductor wafer in one of a plurality of deposition chambers of a processing tool, 0027, where the substrate has openings, abstract, 0027, and Fig. 2a);
conformally depositing a first portion of a material into the feature (depositing a first metal material layer in one of the deposition chambers, 0027, where the first layer of metal fill material is deposited conformally by ALD, 0065, claim 9, and Fig. 2a, and performing a second conformal deposition process such as ALD to deposit a second layer of metal fill material, 0049, claim 9, and Fig. 2c);
after partially depositing the first portion of the material, exposing the substrate to an etching species to etch an angular opening at or near the feature opening to form an etched surface (exposing the surface to a first angled ion beam etching process to remove a portion of the first layer of metal fill material from the upper sidewalls of the opening to increase the opening size 213d proximate the upper corner so as to be larger than the opening size proximate the bottom, 0042-0043, 0047, and Fig. 2b, performing a second angled ion etch process to remove portions of the second layer of metal fill material so that the opening size at the upper corner is larger than the opening size proximate the bottom, 0050, 0052, and Fig. 2e); and
depositing a second portion of the material onto the etched surface to fill the feature (depositing a third metal fill material by ALD or CVD to provide a complete, void-free filling of the opening, 0053 and Fig. 2f).
They depict performing the etching step before a seam forms in the feature, where they indicate that there are openings proximate the upper corner and the bottom (0042, 0046, 0047, 0049, 0052, Fig. 2a and Fig. 2c). From this, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have stopped the deposition and performed the etching process prior to the formation of a void or seam because Babich depicts performing the etching prior to seam or void formation and they indicate that etching is done when there are openings in the upper corner of the opening and proximate the bottom where the process provides void-free filling such that it will be expected to facilitate the filling of the opening while preventing the formation of voids.
Regarding claim 5, Babich suggests the process of claim 1. They further teach placing a wafer in the processing chamber for processing (0027 and 0065). From this, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have performed the process in a single-wafer process chamber because they teach using a wafer as opposed to multiple wafers such that a single-wafer processing chamber is expected to be suitable for the process.
Regarding claim 7, Babich suggests the process of claim 1. They further teach using argon for the ion etching at a pressure of approximately 1x10-4 Torr (0044, 0051), such that the etching species is understood to be oxygen-free since etching is done under low pressure using argon and there is no indication that oxygen is needed or desired.
Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Babich as applied to claim 1 above, and further in view of Jiang, US 2021/0111067 A1.
Regarding claims 4 and 9, Babich suggests the process of claim 1. They teach that the fill material may be deposited by a CVD process (0053), where since they do not indicate it is a PECVD process, it is understood to be a thermal CVD process.
They do not teach performing a post-treatment on the CVD material.
Jiang teaches methods for forming an interconnections structure on a substrate (abstract). They teach forming a barrier layer on a substrate having openings by ALD or CVD (0083, 0088, and Fig. 8). They teach performing a second deposition process to form an interface layer on the barrier layer by CVD or ALD (0092 and Fig. 8). They then fill the gap with metal by a CVD process that includes multiple sub-operations (0095-0096 and Fig. 8). They teach that that the CVD process includes a deposition process and a plasma treatment in the same chamber (0096 and 0098). They teach using precursors for the CVD process that are non-plasma and may include plasmas of the precursors such that when using the non-plasma precursors, the process is understood to be a thermal CVD process (0097). They teach that the plasma treatment process may assist densifying the portion of the gap filling layer formed on the substrate to drive out the defects such as voids, air and impurities from the gap filling layer (0098). They teach that the plasma gas may include at least a hydrogen containing as such as H2, NH3 and the like, and may include an inert gas, such as Ar or He (0100).
From the teachings of Jiang, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have deposited the filling layer by thermal CVD and then to have performed a plasma treatment post-deposition because Babich teaches filling the feature by CVD, which is understood include a thermal CVD process, and Jiang teaches that filling an opening in a feature by CVD is desirably plasma treated to densify the deposited material and remove impurities and air such that it will be expected to also provide the benefits in the CVD filling material of Babich. Therefore, the second portion of the material will be deposited by thermal CVD and a post-treatment process that comprises exposing the substrate to a plasma.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Babich and alternatively rejected over Singhal as applied to claim 1 above, and further in view of Papasouliotis, US 7,482,247 B1.
Regarding claim 6, Singhal or Babich each suggest the process of claim 1.
They do not specifically teach that the process is done without breaking vacuum.
As discussed above for claims 1 and 7, Papasouliotis teaches performing deposition and etch processes where the process is done without breaking vacuum.
From the teachings of Papasouliotis, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Singhal or Babich to have performed the deposition and etch steps without breaking vacuum because Papasouliotis indicates that it is desirable not break vacuum between deposition and etch steps and it will be expected to provide the benefits of not requiring additional pumpdown steps and prevent atmospheric contamination.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Papasouliotis or Babich as applied to claim 1 above, and further in view of Singhal, US 2018/0005801 A1.
Regarding claim 8, Papasouliotis or Babich each suggest the process of claim 1.
They do not teach that the angular opening is etched to a depth of less than about 10% the depth of the feature.
As discussed above, Singhal further teaches that the anisotropic etch can selectively remove more dielectric material near the top of the gap than inside and near the bottom of the gap (0086). They teach that “near the top of the gap” or “near the opening” is defined as an approximate position or an area within the gap corresponding to about 0-10% of the gap depth (0086). Therefore, since more material is removed “near the top of the gap” to provide the sloped edge, the angular opening will be etched in an area corresponding to about 0-10% of the gap depth.
From the teachings of Singhal, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have provided the angular opening to a depth in the range of about 0-10% of the gap depth because Singhal teaches that it is desirable to remove more material at a depth in this range of an opening for preventing seam or void formation such that it will be expected to also provide a suitable depth for preventing voids or seams in the processes of Papasouliotis and Babich. Therefore, the angular opening will be etched to a depth overlapping the claimed range. According to MPEP 2144.05, “in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.”
Conclusion
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/CHRISTINA D MCCLURE/Examiner, Art Unit 1718