DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki US 20200243514 A1 et al hereafter “Yamazaki”.
[Claim 1] Yamazaki teaches a semiconductor device comprising:
a metal oxide (230 fig. 1);
a first conductor (242a fig. 1) and a second conductor (242b fig. 1) over the metal oxide;
a first insulator (272 fig. 1) over the first conductor and the second conductor;
a second insulator (273 fig. 1) over the first insulator;
a third insulator (250 fig. 1) that is between the first conductor and the second conductor and is over the metal oxide;
a third conductor (260a fig. 1) over the third insulator;
a fourth conductor (260b fig. 1) that is over the third conductor and is electrically connected to the third conductor [sufficiently illustrated fig. 1];
a fourth insulator (280 of 600_n+1 relative to 600_n in view of the embodiment of fig. 19 and 17, wherein fig. 19 incorporates element 600 as embodied fig. 17 which incorporates element 200 as embodied fig. 1; fig. 19 illustrates a vertical stack of elements 600 comprising 200) over the fourth conductor;
a fifth insulator (250 of 600_n+1 fig. 19 in view of fig. 17 and 1) provided in a first opening in the fourth insulator [sufficiently illustrated fig. 19]; and
a fifth conductor (260a of 600 n+1 fig. 19 in view of fig. 17 and 1) comprising a region overlapping with the fourth conductor with the fifth insulator therebetween [sufficiently illustrated fig. 19],
wherein the third insulator and the third conductor are provided in a second opening in the first insulator and the second insulator [sufficiently illustrated fig. 1 and 19],
wherein the metal oxide comprises a first region that overlaps with the first conductor
and extends in a first direction [laterally fig. 1 and 17], wherein, in the first region, an end portion of the metal oxide is aligned with an end portion of the first conductor [sufficiently illustrated fig. 1 and 17 at least a left most end and/or edge portions are aligned, see annotation below fig. 1B, fig. 17 illustrates the same end alignment in 200a], and
wherein the first direction is parallel to a direction in which the fifth conductor extends [sufficiently illustrated fig. 1 and 17 met in the same manner as illustrated fig. 12 of the instant application, the fifth conductor extends laterally].
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Annotated fig. 1B; highlighting the end portions and their alignment
[Claim 2] Yamazaki teaches as shown above the semiconductor device according to claim 1, further comprising a sixth conductor (the first conductor of 240 fig. 1, disclosed paragraph 0069 illustrated but not labeled fig. 1), a sixth insulator (241 fig. 1), and a seventh conductor (the second conductor of 240 fig. 1, disclosed paragraph 0069 illustrated but not labeled fig. 1),
wherein the metal oxide comprises a region overlapping with the sixth conductor [sufficiently illustrated fig. 1],
wherein a third opening in the first insulator and the second insulator comprises a region overlapping with the sixth conductor [sufficiently illustrated fig. 1],
wherein the sixth insulator is in contact with a side surface of each of the first insulator and the second insulator in the third opening [sufficiently illustrated fig. 1],
wherein the seventh conductor is provided to fill the third opening with the sixth insulator therebetween [sufficiently illustrated fig. 1], and
wherein the seventh conductor comprises a region in contact with part of a top surface of the sixth conductor and a region in contact with part of a side surface of the sixth conductor [sufficiently illustrated fig. 1 the sixth conductor lines the side and bottom surfaces of the seventh conductor].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki as applied to the claims above, and further in view of US 20200343302 A1 Lee et al hereafter “Lee”.
[Claim 3] Yamazaki teaches as shown above the semiconductor device according to claim 1,
Yamazaki does not teach a seventh insulator
and an eighth insulator, wherein the seventh insulator is between the first conductor and the first insulator, and
wherein the eighth insulator is between the second conductor and the first insulator.
Lee teaches a gate comprising a seventh insulator (126 fig. 3A) is between a first conductor (132 fig. 3A) and a first insulator (comprising 122 and/or 118a-b fig. 3A), and
wherein an eighth insulator (128 fig. 3A) is between a second conductor (136 fig. 3A) and the first insulator.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yamazaki in view of Lee by adding additional gate dielectric layers such that there is “a seventh insulator
and an eighth insulator, wherein the seventh insulator is between the first conductor and the first insulator, and
wherein the eighth insulator is between the second conductor and the first insulator”.
A person of ordinary skill in the art would have been motivated to make this modification to in order to tune the gate dielectric capacitance and subsequent operating voltage of the device [Paragraph 0123 Lee].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki as applied to the claims above, and further in view of US 20120261770 A1 Lin teaches hereafter “Lin”.
[Claim 4] Yamazaki teaches as shown above the semiconductor device according to claim 1,
Yamazaki does not teach the first conductor and the second conductor each have a stacked-layer structure,
wherein the stacked-layer structure comprises a first conductive layer and a second conductive layer over the first conductive layer, and
wherein the first conductive layer comprises a region with a nitrogen concentration higher than a nitrogen concentration in the second conductive layer.
Lin teaches a first conductor (comprising 324, and 328 fig. 8) and the second conductor (330 and 332 fig. 8) each have a stacked-layer structure [sufficiently illustrated fig. 8],
wherein the stacked-layer structure comprises a first conductive layer (324 and 330 fig. 8) and a second conductive layer (328 and 332 fig. 8) over the first conductive layer, and
wherein the first conductive layer comprises a region with a nitrogen concentration higher than a nitrogen concentration in the second conductive layer [132 comprise “aluminum (Al)” paragraph 0019, “low-resistance metal layer” 332 is identical to 132, “top barrier” 330 and/or 130 comprises “titanium nitride (TiN) layer or titanium oxynitride (TiON) layer” paragraph 0019 Al has a lower nitrogen concentration then TiN or TiON, “work function metal layer” 128 and/or 328 discloses with sufficient specificity and embodiment comprising “a titanium tri-aluminide (TiAl.sub.3) single-layered structure, or a Ti/AI bi-layered structure” paragraph 0019, “N-containg layer” 324 and/or 124 comprises TiN and TaN pagraph 0032 and 0033. TiN and TaN have a higher concentration of Nitrogen then TiAl.sub3 and/or Ti/AI].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute and/or combine the first and second conductors of Yamazaki in view of Lin such that they include a barrier layer to layer metal stack “the first conductor and the second conductor each have a stacked-layer structure, wherein the stacked-layer structure comprises a first conductive layer and a second conductive layer over the first conductive layer, and wherein the first conductive layer comprises a region with a nitrogen concentration higher than a nitrogen concentration in the second conductive layer”.
A person of ordinary skill in the art would have been motivated to make this modification to improve the metal diffusion form the metal layers and achieve an ideal work function of the metal gate, and improve the reliability of the gate [paragraph 0036-0037 Lin].
Allowable Subject Matter
Claim 5 and dependent claims allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 5 and dependent claims recite the limitation “a top surface of the fifth conductor is aligned with a top surface of the eighth conductor” noting that as claimed the fifth conductor is a top plate of the first capacitor, the eight conductor is a back gate of the second transistor claimed in “a second metal oxide that is over the eighth conductor and comprises a region overlapping with the eighth conductor”, and the first and second conductors are a front gate and front gate contact/electrode of the first transistor in “a first conductor and a second conductor over the first metal oxide”.
Prior art Yamazaki teaches a semiconductor device comprising: a first transistor (200a of 600_n fig. 19); and
a capacitor (100 fig. 19), a second transistor (200a of 600_n+1 fig. 19), and a fourth insulator (216 of 600_n+1 fig. 19, labeled fig. 1) over the first transistor,
wherein the first transistor comprises: a first metal oxide (230 fig. 1);
a first conductor (243a fig. 1) and a second conductor (243b fig. 1) over the first metal oxide;
a first insulator (272-273 fig. 1) over the first conductor and the second conductor;
a second insulator (280 fig. 1) over the first insulator;
a third insulator (250 fig. 1) that is between the first conductor and the second conductor
and is over the first metal oxide; and a third conductor (260 fig. 1) over the third insulator, wherein the capacitor comprises:
a fourth conductor (204 fig. 1);
a fifth insulator (222 fig. 1) over the fourth conductor; and a fifth conductor (242a fig. 1) comprising a region overlapping with the fourth conductor with the fifth insulator therebetween [sufficiently illustrated fig. 2],
wherein the second transistor comprises: an eighth conductor (205 fig. 1); and a second metal oxide (230 fig. 1) that is over the eighth conductor and comprises a region overlapping with the eighth conductor [sufficiently illustrated fig. 19 in view of fig. 1],
wherein the eighth conductor is provided in a second opening in the fourth insulator [sufficiently illustrated fig. 19 in view of fig. 1].
Yamazaki does not teach the fourth conductor is electrically connected to the third conductor,
wherein the fifth insulator and the fifth conductor are provided in a first opening in the fourth insulator,
wherein a top surface of the fifth conductor is aligned with a top surface of the eighth conductor.
Prior Art US 20160118425 A1 Kurokawa hereafter “Kurokawa” teaches A semiconductor device comprising:
a first transistor (53 fig. 1A); and
a capacitor (59 fig. 1A), a second transistor (52 fig. 1A), and a fourth insulator (42 fig. 1A) over the first transistor,
wherein the first transistor comprises: a first metal oxide (130 fig. 1A, labeled fig. 23B “oxide semiconductor layer” disclosed and metal oxide paragraph 0266);
a first conductor (140 fig. 1A, labeled fig. 23B) and a second conductor (150 fig. 1A, labeled fig. 23B) over the first metal oxide;
a first insulator (175 fig. 1A, labeled fig. 23B) over the first conductor and the second conductor;
a second insulator (180 fig. 1A, labeled fig. 23B) over the first insulator;
a third insulator (160 fig. 1A, labeled fig. 23B) that is between the first conductor and the second conductor and is over the first metal oxide [at least part of 160 is between 140 and 150 under broadest reasonable interpretation, sufficiently illustrated fig. 1A and fig. 23B]; and
a third conductor (170 fig. 1A, labeled fig. 23B) over the third insulator, wherein the capacitor comprises:
a fourth conductor [ sufficiently illustrated fig. 1A in view of the disclosure of “capacitor” wherein the examiner takes the official position that the known structure of a capacitor to one of ordinary skill in the art is conductor-insulator-conductor under broadest reasonable interpretation];
a fifth insulator [sufficiently illustrated fig. 1A in view of the disclosure of “capacitor” see annotation below] over the fourth conductor; and
a fifth conductor [sufficiently illustrated fig. 1A in view of the disclosure of “capacitor” see annotation below] comprising a region overlapping with the fourth conductor with the fifth insulator therebetween [sufficiently illustrated fig. 1A in view of the disclosure of “capacitor” see annotation below],
wherein the fourth conductor is electrically connected to the third conductor [sufficiently illustrated fig. 1A],
wherein the second transistor comprises:
an eighth conductor (173 fig. 1, labeled fig. 38A); and
a second metal oxide (130 fig. 1, labeled fig. 38A) that is over the eighth conductor and comprises a region overlapping with the eighth conductor [sufficiently illustrated fig. 1, in view of fig. 38A],
wherein the fifth insulator and the fifth conductor are provided in a first opening in the fourth insulator [illustrated fig. 1, met under broadest reasonable interpretation, wherein opening includes but not limited ~a cavity~],
Kurokawa does not teach wherein the eighth conductor is provided in a second opening in the fourth insulator, and
wherein a top surface of the fifth conductor is aligned with a top surface of the eighth conductor.
During the course of search the examiner did not find prior art that meets all of the limitations claimed nor sufficient motivation to modify prior art such that all the claim limitations are met, specifically the alignment between the back gate of a second transistor and the capacitor electrically connected to the front gate of a first transistor as claimed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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