DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
EXAMINER'S AMENDMENT
An examiner’s amendment to the record appears below. Should the changes and/or additions be unacceptable to applicant, an amendment may be filed as provided by 37 CFR 1.312. To ensure consideration of such an amendment, it MUST be submitted no later than the payment of the issue fee.
The application has been amended as follows:
Renumber currently amended claim 19 as claim 20.
Renumber new claim 20 as claim 21.
Claim Objections
The numbering of claims is not in accordance with 37 CFR 1.126 which requires the original numbering of the claims to be preserved throughout the prosecution. When claims are canceled, the remaining claims must not be renumbered. When new claims are presented, they must be numbered consecutively beginning with the number next following the highest numbered claims previously presented (whether entered or not).
By the examiner’s amendment set forth above, misnumbered currently amended claim 19 been renumbered claim 20, and misnumbered new claim 20 has been renumbered claim 21.
Drawings
The drawings are objected to because the unlabeled rectangular box(es) shown in the drawings, Figs. 8-9, should be provided with descriptive text labels. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-9, 13-14 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by S. D. Golladay, N. A. Wagner, J. R. Rudert and R. N. Schmidt, "Electron-beam technology for open/short testing of multi-chip substrates," in IBM Journal of Research and Development, vol. 34, no. 2.3, pp. 250-259, March 1990 (Golladay).
Regarding claim 1, Golladay discloses a method of testing a packaging substrate for multi-device in-package integration, with at least one electron beam column (Golladay, e.g., Fig. 1 (duplicated below) and page 251, section entitled “Dual-potential testing (top-to-top nets)”, note multi-chip substrate; note charge beam and read beam in Fig. 1; test method is known as dual potential testing because the primary-beam energy is switched between two different beam potentials; a relatively high-energy beam is used to charge networks, and a lower-energy beam is used for reading net voltages, discharging nets, scanning the insulator, and producing VC images such as those in Figures 1-3), the method comprising:
placing the packaging substrate on a stage in a vacuum chamber (Golladay, e.g., Fig. 4 (duplicated below) and pages 255-256, section entitled “PLI architecture”, placing the packaging substrate on x-y table within a vacuum system; Golladay’s vacuum system implicitly includes a vacuum chamber);
directing an electron beam of the at least one electron beam column with a first landing energy on at least a first portion of the packaging substrate (Golladay, e.g., Fig. 4 and pages 255-256, section entitled “PLI architecture”, note e-beam column disclosed in connection with Fig. 4; also see Fig. 1 and page 251, section entitled “Dual-potential testing (top-to-top nets)”, test method is known as dual potential testing because the primary-beam energy is switched between two different beam potentials; a relatively high-energy beam is used to charge networks, and a lower-energy beam is used for reading net voltages, discharging nets, scanning the insulator, and producing VC images such as those in Figures 1-3; in Golladay’s testing method, the relatively high-energy beam is an electron beam with a first landing energy that is directed on at least a first portion of the packaging substrate as claimed);
directing the electron beam of the at least one electron beam column with a second landing energy different from the first landing energy on the packaging substrate (see Golladay as discussed above, Fig. 1 and page 251, section entitled “Dual-potential testing (top-to-top nets)”, test method is known as dual potential testing because the primary-beam energy is switched between two different beam potentials; a relatively high-energy beam is used to charge networks, and a lower-energy beam is used for reading net voltages, discharging nets, scanning the insulator, and producing VC images such as those in Figures 1-3); in Golladay’s testing method, the lower-energy beam is an electron beam with a second landing energy different from the first landing energy directed on the packaging substrate as claimed); and
detecting signal electrons emitted upon impingement of the electron beam for testing at least a first device-to-device electrical interconnect path of the packaging substrate (Golladay, e.g., Fig. 4 and pages 255-256, section entitled “PLI architecture”, note SE voltage-contrast detector disclosed in connection with Fig. 4; also see page 251, section entitled “Electron-beam test method”, Node voltages are measured or read by analyzing the kinetic energy of the SE and thereby the electrostatic potential of their point of origin; intensity modulation of the SE signal arising from voltage differences is called voltage contrast).
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Regarding claim 2, Golladay discloses wherein directing the electron beam with the second landing energy is provided on a second portion of the packaging substrate and the detecting of the signal electrons is provided upon impingement of the electron beam with the second landing energy (see Golladay as applied to claim 1, e.g., Fig. 1 and page 251, section entitled “Dual-potential testing (top-to-top nets)”, test method is known as dual potential testing because the primary-beam energy is switched between two different beam potentials; a relatively high-energy beam is used to charge networks, and a lower-energy beam is used for reading net voltages, discharging nets, scanning the insulator, and producing VC images such as those in Figures 1-3; note read beam in Fig. 1).
Regarding claim 3, Golladay discloses wherein the first portion and the second portion are different (see Golladay as applied to claim 1, e.g., Fig. 1 and page 251, section entitled “Dual-potential testing (top-to-top nets)”, test method is known as dual potential testing because the primary-beam energy is switched between two different beam potentials; a relatively high-energy beam is used to charge networks, and a lower-energy beam is used for reading net voltages, discharging nets, scanning the insulator, and producing VC images such as those in Figures 1-3; note charge and read beams in Fig. 1 are directed on different first and second portions of the of the packaging substrate).
Regarding claim 6, Golladay discloses directing the electron beam of the at least one electron beam column with a fourth landing energy different from the first landing energy on the first portion of the packaging substrate for discharging of the first portion (see Golladay as applied to claim 1, e.g., Fig. 1 and page 251, section entitled “Electron-beam test method”, the e-beam
substrate tester is fundamentally different in that it uses the electron beam to charge or discharge nets; test method is known as dual potential testing because the primary-beam energy is switched between two different beam potentials; a relatively high-energy beam is used to charge networks, and a lower-energy beam is used for reading net voltages, discharging nets, scanning the insulator, and producing VC images such as those in Figures 1-3).
Regarding claim 7, Golladay discloses wherein the electron beam is focused while directing the electron beam with the first landing energy, with the second landing energy, and for detecting the signal electrons (Golladay, e.g., Fig. 4 and pages 255-256, section entitled “PLI architecture”; function of the e-beam column is to
generate, focus, and deflect the primary beam, and to detect secondary electrons produced when the primary beam strikes the substrate; also note lenses/projection lens in Fig. 4).
Regarding claim 8, Golladay discloses scanning the electron beam to one or more positions on the packaging substrate for charging and for detecting the signal electrons (Golladay, e.g., Fig. 4 and pages 255-256, section entitled “PLI architecture”, a deflection control unit to provide raster scanning or vector beam addressing).
Regarding claim 9, Golladay discloses wherein the packaging substrate comprises a plurality of device-to-device electrical interconnect paths extending between respective first surface contact points and second surface contact points (Golladay, e.g., Fig. 1), the method further comprising: testing the plurality of device-to-device electrical interconnect paths sequentially and/or in parallel (Golladay, e.g., Fig. 4 and pages 255-256, section entitled “PLI architecture”, a deflection control unit to provide raster scanning or vector beam addressing; the examiner notes that raster scanning and vector beam addressing are examples of sequential scanning techniques).
Regarding claim 13, Golladay discloses wherein the packaging substrate comprises 5.000 or more device-to-device electrical interconnect paths which are all tested (Golladay, e.g. pages 251-252, section entitled “Testing for shorts”, a typical high-performance substrate might have 10,000 nets averaging only three nodes per net; also see page 254, section entitled “E-beam tester throughput”, assuming 5-ms charge times, a substrate containing 10,000 nets in 30,000 nodes could be tested in approximately two minutes).
Regarding claim 14, Golladay discloses:
obtaining information about one or more electric potentials from an energy of the signal electrons (Golladay, e.g., Fig. 4 and pages 255-256, section entitled “PLI architecture”, the test control program uses a standard format net list which describes the configuration of each net and the location of each accessible net node; using the net list and various application programs, the main test program performs read and charge functions to detect open and short defects); and
determining from the information if the first device-to-device electrical interconnect path is defective (Golladay, e.g., Fig. 4 and pages 255-256, section entitled “PLI architecture”, the test control program uses a standard format net list which describes the configuration of each net and the location of each accessible net node; using the net list and various application programs, the main test program performs read and charge functions to detect open and short defects).
Regarding claim 16, Golladay discloses wherein the testing comprises determining if the first device-to-device electrical interconnect path has one or more of the following defects: a short, an open, and/or a leakage (Golladay, e.g., Fig. 4 and pages 255-256, section entitled “PLI architecture”, the test control program uses a standard format net list which describes the configuration of each net and the location of each accessible net node; using the net list and various application programs, the main test program performs read and charge functions to detect open and short defects).
Regarding claim 17, Golladay discloses an apparatus for testing a packaging substrate in accordance with the method of claim 1 (Golladay, e.g., Fig. 4 and pages 255-256, section entitled “PLI architecture”).
Regarding claim 18, Golladay discloses an apparatus for contactless testing of a packaging substrate for multi-device in-package integration, comprising:
a vacuum chamber (Golladay, e.g., Fig. 4 (duplicated above in connection with claim 1) and pages 255-256, section entitled “PLI architecture”, placing the packaging substrate on x-y table within a vacuum system; Golladay’s vacuum system implicitly includes a vacuum chamber);
a stage within the vacuum chamber, the stage being configured to support the packaging substrate (Golladay, e.g., Fig. 4 (duplicated above in connection with claim 1) and pages 255-256, section entitled “PLI architecture”, placing the packaging substrate on x-y table within a vacuum system; Golladay’s x-y table constitutes a stage as claimed);
a charged particle beam column configured to generate an electron beam (Golladay, e.g., Fig. 4 and pages 255-256, section entitled “PLI architecture”, note e-beam column disclosed in connection with Fig. 4), the charged particle electron beam column comprising:
an objective lens configured to focus the electron beam on the packaging substrate (Golladay, e.g., Fig. 4 and pages 255-256, section entitled “PLI architecture”, projection lens);
a scan deflector configured to scan the electron beam to different positions on the packaging substrate (Golladay, e.g., Fig. 4 and pages 255-256, section entitled “PLI architecture”, deflection control unit to provide raster scanning);
an electron detector for detecting signal electrons emitted upon impingement of the electron beam on the packaging substrate (Golladay, e.g., Fig. 4 and pages 255-256, section entitled “PLI architecture”, note SE voltage-contrast detector disclosed in connection with Fig. 4; also see page 251, section entitled “Electron-beam test method”, Node voltages are measured or read by analyzing the kinetic energy of the SE and thereby the electrostatic potential of their point of origin; intensity modulation of the SE signal arising from voltage differences is called voltage contrast); and
one or more power supplies to vary a landing energy of the electron beam (Golladay, e.g., Fig. 4 and pages 255-256, section entitled “PLI architecture”, column is reconfigured to support dual-potential operation; beam energy is switched by a fast high-voltage FET switch; also see Fig. 1 and page 251, section entitled “Dual-potential testing (top-to-top nets)”, test method is known as dual potential testing because the primary-beam energy is switched between two different beam potentials; a relatively high-energy beam is used to charge networks, and a lower-energy beam is used for reading net voltages, discharging nets, scanning the insulator, and producing VC images such as those in Figures 1-3); the apparatus further comprising:
an analysis unit for determining, based on the signal electrons, if a first device-to-device electrical interconnect path is defective (Golladay, e.g., Fig. 4 and pages 255-256, section entitled “PLI architecture”; the test control program uses a standard format net list which describes the configuration of each net and the
location of each accessible net node; using the net list and various application programs, the main test program performs read and charge functions to detect open and short defects).
Regarding claim 19, Golladay discloses a scan controller configured for directing the electron beam of the charged particle electron beam column with a first landing energy on at least a first portion of the packaging substrate, the first portion comprising a surface contact point of a first device-to-device electrical interconnect path of the packaging substrate, wherein the electron beam is vector scanned to the surface contact point for charging the surface contact point: and wherein the scan controller is further configured for directing the electron beam of the charged particle beam column with a second landing energy different from the first landing energy on the packaging substrate (Golladay, e.g., Fig. 4 and pages 255-256, section entitled “PLI architecture”, note e-beam column disclosed in connection with Fig. 4; also see Fig. 1 and page 251, section entitled “Dual-potential testing (top-to-top nets)”, test method is known as dual potential testing because the primary-beam energy is switched between two different beam potentials; a relatively high-energy beam is used to charge networks, and a lower-energy beam is used for reading net voltages, discharging nets, scanning the insulator, and producing VC images such as those in Figures 1-3; in Golladay’s testing arrangement, the relatively high-energy beam is an electron beam with a first landing energy that is directed on at least a first portion of the packaging substrate and the lower-energy beam is an electron beam with a second landing energy different from the first landing energy directed on the packaging substrate; also see page 255, PLl tool is controlled by a computer which communicates with a deflection control unit to provide raster scanning, vector beam addressing, and the capture of voltage-level feedback data for imaging or testing; Golladay’s computer constitutes a scan controller that may utilize vector beam addressing to control beam placement; also see Fig. 1 which discloses directing the electron beam of the charged particle electron beam column with the first landing energy (charge beam) on at least the first portion of the packaging substrate, the first portion comprising a surface contact point of a first device-to-device electrical interconnect path of the packaging substrate, and directing the electron beam of the charged particle beam column with the second landing energy (read beam) different from the first landing energy on the packaging substrate).
Regarding claim 20, Golladay discloses wherein the first portion comprising a surface contact point of the first device-to-device electrical interconnect path of the packaging substrate, wherein the electron beam is vector scanned to the surface contact point for charging the surface contact point (see Golladay as applied to claim 1, e.g., Fig. 1 discloses that the first portion includes a surface contact point of the first device-to-device electrical interconnect path of the packaging substrate, wherein the electron beam (charge beam) is scanned to the surface contact point for charging the surface contact point; also see page 255, PLl tool is controlled by a computer which communicates with a deflection control unit to provide raster scanning, vector beam addressing, and the capture of voltage-level feedback data for imaging or testing).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Golladay in view of US 2021/0233859 to Lee et al. (Lee).
Regarding claims 10-12, Golladay is not relied upon as explicitly disclosing wherein the first surface contact points and the second surface contact points have a diameter of 25 μm or less (claim 10), wherein the first surface contact points and the second surface contact points are formed as a metal pad covered by a solder bump having a diameter of 25 μm or less (claim 11) and wherein the first surface contact points and the second surface contact points have a three-dimensional topography (claim 12). Lee discloses in Fig. 6C and paragraphs 72-75 a back-side wiring substrate 100 that includes first and second surface contact points in the form of bump type connectors 201 having a diameter or horizontal width of 10 μm to 300 μm. Similarly, Fig. 7B and paragraphs 76-78 disclose first and second surface contact points in the form of ball type connectors 202 comprising solder 210 formed on a back-side wiring substrate 100. In Fig. 7B, ball type connectors 202 are attached by a reflow process, which implies the presence of a metal pad under each ball type connectors 202. In each of Figs. 6C and 7B, the bump type connectors 201 and ball type connectors 202 have a three-dimensional topography. Lee therefore at least suggests packaging substates having the features of claims 10-12. The prior art therefore included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately. Moreover, one of ordinary skill in the art would have recognized that the results of the combination were predictable. For these reasons, recitations wherein the first surface contact points and the second surface contact points have a diameter of 25 μm or less (claim 10), wherein the first surface contact points and the second surface contact points are formed as a metal pad covered by a solder bump having a diameter of 25 μm or less (claim 11) and wherein the first surface contact points and the second surface contact points have a three-dimensional topography (claim 12) do not patentably define over Golladay when considered in light of the teachings of Lee.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Golladay in view of US 2002/0161534 to Adler et al. (Adler).
Regarding claim 15, Golladay is not relied upon as explicitly disclosing wherein obtaining the information comprises: energy filtering the signal electrons. In related art, Adler discloses selection of secondary electrons or backscattered electrons may be made by use of an energy filter on or before the detector (Adler, e.g., paragraph 59). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Golladay such that obtaining the information comprises energy filtering the signal electrons. In this way, in the manner disclosed by Adler, selection of secondary electrons or backscattered electrons for detection may be implemented.
Allowable Subject Matter
Claims 4-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 8,113,412 to Tseng et al. relates to a method that includes electrically grounding a first plurality of metal bumps on a first surface of an interconnection component to a common ground plate. A voltage contrast (VC) image of a second plurality of metal bumps of the interconnection component is generated. Grey levels of the second plurality of metal bumps in the VC image are analyzed to find defect connections between the second plurality of metal bumps and respective ones of the first plurality of metal bumps.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL R MILLER whose telephone number is (571)270-1964. The examiner can normally be reached 9AM-5PM EST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak, can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL R MILLER/Primary Examiner, Art Unit 2858
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