DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on November 14, 2024 has been considered by the Examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Satoshi (JP 2012-209418; cited in the IDS).
Regarding claim 1, Satoshi discloses a printed circuit board (10; see figure 1) comprising: a wiring portion (2; see figure 1) comprising a wiring layer; and an electrode pad (3) provided on the wiring portion (2; see figure 1) and connected to the wiring layer (see figure 1), wherein a connection surface that is a surface of the electrode pad (3) on a side opposite to the wiring portion has an arithmetic mean roughness Ra of 0.5 µm or more and 2.0 µm or less (paragraph 0029 and 0044).
Regarding claim 2, Satoshi discloses the printed circuit board (10; see figure 1), wherein a number of protrusions having a height exceeding 3 µm on the connection surface is 5 or less per 15 µm length in an in-plane direction of the connection surface (paragraph 0044-0045).
Regarding claim 3, Satoshi discloses the printed circuit board (10; see figure 1), further comprising a surface insulating resin layer (5) provided on a surface of the wiring portion (2; see figure 1) on the electrode pad (3) side and having an opening configured to expose the electrode pad (3), wherein the surface insulating resin layer (5) is in contact with a part of the connection surface (see figure 2).
Regarding claim 4, Satoshi discloses the printed circuit board (10; see figure 1), wherein the surface insulating resin layer (5) is a layer formed of a thermosetting or photocurable resist material comprising an epoxy resin (paragraph 0023).
Regarding claim 5, Satoshi discloses a semiconductor device (see figure 1) comprising: the printed circuit board (see figure 1; 10); and a semiconductor chip (S) mounted on the printed circuit board (paragraph 0015; see figure 1).
Regarding claim 6, Satoshi discloses a method for manufacturing a printed circuit board (10; see figure 1), the method comprising: preparing a wiring structure (2) comprising a wiring portion comprising a wiring layer (see figure 1) and an electrode pad (3) provided on the wiring portion (see figure 1); and processing a connection surface that is a surface of the electrode pad on a side opposite to the wiring portion so that the connection surface has a surface having an arithmetic mean roughness Ra of 0.5 µm or more and 2.0 µm or less (paragraph 0029 and 0044).
Regarding claim 7, Satoshi discloses the method (see figure 1), wherein the connection surface is processed to have a surface having an arithmetic mean roughness Ra of 0.5µm or more and 2.0 µpm or less, and to have a number of protrusions with a height exceeding 3µm of 5 or fewer per 15 µm length in an in-plane direction of the connection surface (paragraph 0029, 0044 and 0045).
Regarding claim 8, Satoshi discloses the method (see figure 1), further comprising: forming a surface insulating resin layer (5) having an opening configured to expose the connection surface on a surface of the wiring portion (2) on the electrode pad side (3), wherein the surface insulating resin layer is formed so as to be in contact with a part of the connection surface (see figure 1).
Regarding claim 9, Satoshi discloses the method (see figure 1), wherein the surface insulating resin layer (5) is formed of a thermosetting or photocurable resist material comprising an epoxy resin (paragraph 0023).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Park et al (US 11,627,659), Song et al (US 9,502,341), Takakura (US 9,173,301) and Lee et al (US 12,495,496) disclose a printed circuit board.
5. Any inquiry concerning this communication should be directed to Angel R. Estrada at telephone number (571) 272-1973. The Examiner can normally be reached on Monday-Friday (8:30am -5:00pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Imani N. Hayman can be reached on (571) 270-5528. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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June 27, 2006
/ANGEL R ESTRADA/Primary Examiner, Art Unit 2841
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