DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 5, 8 and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Showa (WO 2022/054873 A1; English Translation provided by Applicant).
Regarding Claim 1, Showa (WO 2022/054873 A1; English Translation provided by Applicant) discloses a method (Fig 1) for manufacturing a wiring board (10), the method comprising: providing a resist layer (3) on a seed layer (20) comprising a metal ([0046]), the seed layer (20) being provided on a main surface of a substrate (1); forming a pattern (at 2) including an opening (3A) through which the seed layer (20) is exposed at the resist layer (3) by exposure and development of the resist layer; and forming a copper plating layer (21) comprising a portion having a width of less than 10 μm ([0047] “5 to 20 μm”) on the seed layer (20) exposed in the opening by electrolytic plating ([0046-0048]), wherein the copper plating layer (21) is formed so that a BP occupancy that is an occupancy of a black portion ([0048] “black portions”) observed in a cross section of a metal portion (about 2) comprising the seed layer (20) and the copper plating layer (21) in a width direction of the copper plating layer, is 45% or less ([0048] “8 or less per 1 μm”), and the BP occupancy is a value as determined by a method comprising: determining a number n of black portions observed in a region ([0048] “8 or less per 1 μm”) having a width of L [μm] ([0048]) in a direction parallel to the main surface of the substrate (1) in a cross section of the metal portion comprising the copper plating layer having a width of less than 10 μm ([0048]); determining a maximum width wi [μm] ([0048] “maximum width of less than 0.3 μm”) of each of the n black portions in a direction parallel to the main surface of the substrate; and calculating the BP occupancy according to a following equation:
BP occupancy (%) =
∑
i
=
1
n
W
i
×
1
L
×
100
Regarding Claim 2, Showa further discloses the method (Fig 1) according to claim 1, further comprising: removing (Fig 1(d)- Fig 1(e)) the resist layer (3) to expose a portion of the seed layer (20) that is not covered with the copper plating layer (21); and removing (Fig 1(e)) an exposed portion of the seed layer (20) with an etching liquid to form a wiring board comprising: a wiring comprising the seed layer and the copper plating layer; and the substrate.
Regarding Claim 3, Showa further discloses the method (Fig 1) according to claim 1, wherein the resist layer comprises a binder polymer ([0015]), a photopolymerizable component ([0015]), and a photopolymerization initiator ([0015]), and the resist layer is selected so that the BP occupancy is 45% or less ([0048]).
Regarding Claim 4, Showa further discloses the method (Fig 1) according to claim 3, wherein the photopolymerization initiator comprises a 2,4,5-triarylimidazole dimer derivative ([0029]).
Regarding Claim 5, Showa further discloses the method (Fig 1) according to claim 4, wherein a content of the 2,4,5-triarylimidazole dimer derivative in the resist layer is selected in a range of 6 parts by mass or more and 12 parts by mass or less with respect to 100 parts by mass ([0030]) of a total amount of the binder polymer and the photopolymerizable component.
Regarding Claim 8, Showa (WO 2022/054873 A1; English Translation provided by Applicant) a method (Fig 1) for evaluating a wiring board comprising: a substrate (10); and a wiring (2) provided on the substrate (10), wherein the wiring (2) comprises: a seed layer (20) provided on the substrate (1); and a copper plating layer (21) comprising a portion having a width of less than 10 μm ([0047] “5 to 20 μm”), the copper plating layer (21) being formed on the seed layer (20), the method comprises determining a BP occupancy ([0048] “black portions”) that is an occupancy of a black portion observed in a cross section of the wiring in a width direction of the copper plating layer, and a method for determining the BP occupancy comprises: determining a number n of black portions ([0048] “8 or less per 1 μm”) observed in a region having a width of L [μm] ([0048]) in a direction parallel to a main surface of the substrate in a cross section of the wiring comprising the copper plating layer having a width of less than 10 μm ([0048]); determining a maximum width wi [μm] ([0048] “maximum width of less than 0.3 μm”) of each of the n black portions in a direction parallel to the main surface of the substrate; and calculating the BP occupancy ([0048] “8 or less per 1 μm”) according to a following equation:
BP occupancy (%) =
∑
i
=
1
n
W
i
×
1
L
×
100
Regarding Claim 9, Showa (WO 2022/054873 A1; English Translation provided by Applicant) discloses a wiring board (Fig 1) comprising: a substrate (1); and a wiring (2) provided on the substrate (1), wherein the wiring (2) comprises: a seed layer (20) provided on the substrate (1); and a copper plating layer (21; [0046]) comprising a portion having a width of less than 10 μm ([0047] “5 to 20 μm”), the copper plating layer (21) being formed on the seed layer (20), a BP occupancy that is an occupancy of a black portion ([0048] “black portions”) observed in a cross section of the wiring in a width direction of the copper plating layer, is 45% or less ([0048] “8 or less per 1 μm”), and the BP occupancy is a value as determined by a method comprising: determining a number n of black portions observed in a region ([0048] “8 or less per 1 μm”) having a width of L [μm] ([0048]) in a direction parallel to a main surface of the substrate in a cross section of the wiring comprising the copper plating layer (21) having a width of less than 10 μm ([0048]); determining a maximum width wi [μm] ([0048] “maximum width of less than 0.3 μm”) of each of the n black portions in a direction parallel to the main surface of the substrate; and calculating the BP occupancy according to a following equation:
BP occupancy (%) =
∑
i
=
1
n
W
i
×
1
L
×
100
Claim(s) 8 and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hidani (US 2023/0371176 A1).
Regarding Claim 8, Hidani (US 2023/0371176 A1) discloses a method (Fig 2) for evaluating ([0118]) a wiring board comprising: a substrate (1); and a wiring (2) provided on the substrate (1), wherein the wiring comprises: a seed layer (4,5) provided on the substrate (1); and a copper plating layer (6) comprising a portion having a width of less than 10 μm ([0079] “10 μm or less”), the copper plating layer (6) being formed on the seed layer (4,5), the method comprises determining ([0118-0133]) a BP occupancy that is an occupancy of a black portion ([0084-0090] “voids”; note that the Applicant’s Specification states at [0012] “inventors infer that the black portion is some defective portion such as a minute void, which is related to adhesion between the copper plating layer 21 and the seed layer 20” and thus the claimed black portion are voids) observed in a cross section of the wiring in a width direction of the copper plating layer (6), and a method for determining ([0118-0133]) the BP occupancy comprises: determining a number n of black portions ([0085-0090,0121-0133] “voids is 0”) observed in a region ([0084-0090] “number of voids generated in base film 1 is 10 or less per a reference unit area D of 0.25 mm.sup.2 on the surface of the base film. The number of voids per reference unit area D may be 5 or less, or may be 1 or less. Preferably, the number of voids is 0”) having a width of L [μm] ([0121] “number N of voids per reference unit area D was determined by calculation of T/(X/D) because a region having a width X corresponding to 0.02 mm.sup.2 of the surface of the base film appears in the metallurgical microscope image”) in a direction parallel to a main surface of the substrate in a cross section of the wiring comprising the copper plating layer (6) having a width of less than 10 μm ([0082-0090,0121-0133]); determining a maximum width wi [μm] ([0082-0090,0121-0133] “maximum width”) of each of the n black portions in a direction parallel to the main surface of the substrate; and calculating the BP occupancy according to a following equation:
BP occupancy (%) =
∑
i
=
1
n
W
i
×
1
L
×
100
Regarding Claim 9, Hidani (US 2023/0371176 A1) discloses a wiring board (Fig 1) comprising: a substrate (1); and a wiring (2) provided on the substrate (1), wherein the wiring (2) comprises: a seed layer (4,5) provided on the substrate (1); and a copper plating layer (6) comprising a portion having a width of less than 10 μm ([0079] “10 μm or less”), the copper plating layer (6) being formed on the seed layer (4,5), a BP occupancy that is an occupancy of a black portion ([0084-0090] “voids”; note that the Applicant’s Specification states at [0012] “inventors infer that the black portion is some defective portion such as a minute void, which is related to adhesion between the copper plating layer 21 and the seed layer 20” and thus the claimed black portion are voids) observed in a cross section of the wiring in a width direction of the copper plating layer, is 45% or less ([0085-0090,0121-0133] “voids is 0”), and the BP occupancy is a value as determined by a method comprising: determining a number n of black portions observed in a region ([0084-0090] “number of voids generated in base film 1 is 10 or less per a reference unit area D of 0.25 mm.sup.2 on the surface of the base film. The number of voids per reference unit area D may be 5 or less, or may be 1 or less. Preferably, the number of voids is 0”) having a width of L [μm] ([0121] “number N of voids per reference unit area D was determined by calculation of T/(X/D) because a region having a width X corresponding to 0.02 mm.sup.2 of the surface of the base film appears in the metallurgical microscope image”) in a direction parallel to a main surface of the substrate in a cross section of the wiring comprising the copper plating layer (6) having a width of less than 10 μm ([0082-0090,0121-0133]); determining a maximum width wi [μm] ([0082-0090,0121-0133] “maximum width”) of each of the n black portions in a direction parallel to the main surface of the substrate; and calculating the BP occupancy according to a following equation:
BP occupancy (%) =
∑
i
=
1
n
W
i
×
1
L
×
100
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 – 6 are rejected under 35 U.S.C. 103 as being unpatentable over Hidani (US 2023/0371176 A1) in view of Okade (US 2017/0261851 A1).
Regarding Claim 1, Hidani (US 2023/0371176 A1) discloses a method (Fig 2) for manufacturing a wiring board (300), the method comprising: providing a resist layer ([0082-0083]), a seed layer (4,5) comprising a metal ([0043,0066,0067]), the seed layer (4,5) being provided on a main surface of a substrate (1); forming a pattern (at 2; [0082] “patterning corresponding to the conductive pattern is performed on the resist by exposure, development, and the like. Subsequently, portions of conductor layer 2 other than the conductive pattern are removed by etching using the patterned resist as a mask”) and development of the resist layer ([0082] “patterning corresponding to the conductive pattern is performed on the resist by exposure, development, and the like. Subsequently, portions of conductor layer 2 other than the conductive pattern are removed by etching using the patterned resist as a mask”); and forming a copper plating layer (6) comprising a portion having a width of less than 10 μm ([0079] “10 μm or less”) on the seed layer (4,5) exposed in the opening by electrolytic plating ([0075-0083]), wherein the copper plating layer (6) is formed so that a BP occupancy that is an occupancy of a black portion ([0084-0090] “voids”; note that the Applicant’s Specification states at [0012] “inventors infer that the black portion is some defective portion such as a minute void, which is related to adhesion between the copper plating layer 21 and the seed layer 20” and thus the claimed black portion are voids) observed in a cross section (D) of a metal portion (about 2) comprising the seed layer (4-5) and the copper plating layer (6) in a width direction of the copper plating layer, is 45% or less ([0085-0090,0121-0133] “voids is 0”), and the BP occupancy is a value as determined by a method comprising: determining a number n of black portions observed in a region ([0084-0090] “number of voids generated in base film 1 is 10 or less per a reference unit area D of 0.25 mm.sup.2 on the surface of the base film. The number of voids per reference unit area D may be 5 or less, or may be 1 or less. Preferably, the number of voids is 0”) having a width of L [μm] ([0121] “number N of voids per reference unit area D was determined by calculation of T/(X/D) because a region having a width X corresponding to 0.02 mm.sup.2 of the surface of the base film appears in the metallurgical microscope image”) in a direction parallel to the main surface of the substrate (1) in a cross section of the metal portion comprising the copper plating layer having a width of less than 10 μm ([0082-0090,0121-0133]); determining a maximum width wi [μm] ([0082-0090,0121-0133] “maximum width”) of each of the n black portions in a direction parallel to the main surface of the substrate; and calculating the BP occupancy according to a following equation:
BP occupancy (%) =
∑
i
=
1
n
W
i
×
1
L
×
100
.
Hidani does not explicitly disclose providing a resist layer on a seed layer comprising a metal, the seed layer being provided on a main surface of a substrate; forming a pattern including an opening through which the seed layer is exposed at the resist layer by exposure and development of the resist layer.
Okade (US 2017/0261851 A1) teaches of a method (Fig 2) for manufacturing a wiring board, the method comprising: providing a resist layer (32) on a seed layer (10) comprising a metal ([0144]), the seed layer (10) being provided on a main surface of a substrate (15); forming a pattern (Fig 2(c)) including an opening (see Fig 2(d)) through which the seed layer (10) is exposed at the resist layer by exposure and development ([0144]) of the resist layer; and forming a copper plating layer (42; [0095,0139,0144]) comprising a portion having a width of less than 10 μm ([0195]) on the seed layer exposed in the opening by electrolytic plating.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the method as disclosed by Hidani, providing a resist layer on a seed layer comprising a metal, the seed layer being provided on a main surface of a substrate; forming a pattern including an opening through which the seed layer is exposed at the resist layer by exposure and development of the resist layer as taught by Okade, in order to allow formation of finer circuit patterns, improve production efficiency and improve sensitivity (Okade, [0002-0009]).
Regarding Claim 2, Hidani in view of Okade teaches the limitations of the preceding claim.
Okade further teaches the method (Fig 2) comprising: removing (Fig 2(c)) the resist layer (32) to expose a portion of the seed layer (10) that is not covered with the copper plating layer (40; [0095,0139]); and removing (Fig 2(f)) an exposed portion of the seed layer (10) with an etching liquid ([0138]) to form a wiring board comprising: a wiring (10,40) comprising the seed layer (10) and the copper plating layer (40); and the substrate (15).
Regarding Claim 3, Hidani in view of Okade teaches the limitations of the preceding claim.
Hidani further discloses the method according to claim 1 wherein the resist layer ([0082]) is selected so that the BP occupancy is 45% or less ([[0084-0090]]).
Hidani does not disclose the method according to claim 1, wherein the resist layer comprises a binder polymer, a photopolymerizable component, and a photopolymerization initiator.
Okade further teaches of the method (Fig 2), wherein the resist layer (32) comprises a binder polymer ([0011]), a photopolymerizable component ([0011]), and a photopolymerization initiator ([0011]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the method as taught by Hidani in view of Okade, wherein the resist layer comprises a binder polymer, a photopolymerizable component, and a photopolymerization initiator as taught by Okade, in order to provide excellent sensitivity, provide improve adhesion, provide improve release property and allow a formation of resist pattern having L/S of 10/10 or less () (Okade, [0012-0016]).
Regarding Claim 4, Hidani in view of Okade teaches the limitations of the preceding claim.
Okade further teaches the method (Fig 2) according to claim 3, wherein the photopolymerization initiator comprises a 2,4,5-triarylimidazole dimer derivative ([0015,0071,0077]).
Regarding Claim 5, Hidani in view of Okade teaches the limitations of the preceding claim.
Okade further teaches the method (Fig 2) according to claim 4, wherein a content ([0079]) of the 2,4,5-triarylimidazole dimer derivative in the resist layer is selected in a range of 6 parts by mass or more and 12 parts by mass or less with respect to 100 parts by mass of a total amount of the binder polymer and the photopolymerizable component.
Regarding Claim 6, Hidani in view of Okade teaches the limitations of the preceding claim.
Okade further teaches the method (Fig 2) according to claim 3, wherein the photopolymerizable component comprises a photopolymerizable compound having an oxyalkylene group ([0050-0069]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sakai (US 2021/0153358 A1) teaches of a method (Fig 2) for manufacturing a wiring board, the method comprising: providing a resist layer (R) on a seed layer (11a,11c), the seed layer (11) being provided on a main surface of a substrate (1); forming a pattern including an opening (Fig 2D) through which the seed layer is exposed at the resist layer by exposure and development of the resist layer; and forming a copper plating layer (11b; [0040]) comprising a portion having a width of less than 10 μm (Abstract) on the seed layer exposed in the opening by electrolytic plating, wherein the copper plating layer is formed so that a BP occupancy that is an occupancy of a black portion ([0046-0048]) observed in a cross section of a metal portion comprising the seed layer and the copper plating layer in a width direction of the copper plating layer, is 45% or less. This could be used in a future 103 Rejection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ROSHN K VARGHESE/Primary Examiner, Art Unit 2847
Prosecution Insights