Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in JAPAN on 09/26/2022.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 12/18/2024 has/have been considered by the examiner and made of record in the application file.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed details of claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
As an example, the claims currently recite the following limitations which are not shown in the drawings:
A semiconductor wafer including a plurality of electrodes on one of main surfaces;
A stacked body, including a bonding adhesive layer, on the semiconductor wafer on a side in which the electrode(s) is/are provided;
Grinding the semiconductor wafer on a side opposite to the side in which the electrode is provided to make the semiconductor wafer thin;
Dicing the thinned semiconductor wafer and the bonding adhesive layer into a chip;
Electrically connecting an electrode of the semiconductor chip with the bonding adhesive layer to an electrode of another semiconductor chip or wiring circuit board.
All of these limitations which are not shown in the drawings are problematic as it results in a lack of clarity for several features and/or steps. For example, the claim and specification seem to suggest that the stacked body, including the adhesives, is formed on the same side of the semiconductor wafer as the electrodes and completely covers, or at least nearly completely covers, the indicated side based on the claimed diameters of the stacked body and the wafer. It becomes unclear then, due to a lack of drawings, how one may electrically connect the electrode(s) to another chip if the adhesive is still present covering that side of the chip/wafer.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is generally narrative and indefinite, failing to conform with current U.S. practice. It appears to be a literal translation into English from a foreign document and is replete with grammatical and idiomatic errors. The examiner has provided suggested amendments below (bolded and underlined) to resolve identified issues along with brief explanations (italicized) for why the amendments are necessary and/or suggested to render the claim(s) definite.
Claim 1. A method for manufacturing a semiconductor device, comprising:
preparing a semiconductor wafer including a plurality of electrodes on a first side of the semiconductor wafer (it is otherwise unclear what the main surfaces are of since no mention is made to the semiconductor wafer and these could be main surfaces of anything) to stick a stacked body, which includes a backgrind tape including a base material and a pressure-sensitive adhesive layer formed on the base material, and a bonding adhesive layer formed on the pressure-sensitive adhesive layer, onto the semiconductor wafer on [[a]] the first side (previous recitation was to a main surface such that “a side” is unclear, with amendments as above this becomes a first side) in which the electrodes are (recitation has only been made to a plurality of electrodes, no recitation has been made to a singular electrode, whether part of the plurality or not) provided (this limitation is unclear as it seems to reference another side but it is not clear if this is a side of the adhesive layer or the wafer);
grinding the semiconductor wafer on a second side (necessary to differentiate from the first side) opposite to the side in which the electrodes are (recitation has only been made to a plurality of electrodes, no recitation has been made to a singular electrode, whether part of the plurality or not) provided to make the semiconductor wafer [[thin]] thinner (thin is a relative term that requires some boundary before which the wafer was not “thin” and this boundary has not been provided by the application or claims such that one of ordinary skill in the art does not have a reasonable understanding of what point in grinding the wafer has been made “thin”, in the alternative thinner is clear as it only requires the wafer to be thinner than it was prior to grinding);
dicing the thinned semiconductor wafer and the bonding adhesive layer to be singulated into a semiconductor chip with the bonding adhesive layer; and
electrically connecting an electrode of the electrodes (recitation has only been made to a plurality of electrodes, no recitation has been made to a singular electrode, whether part of the plurality or not) of the semiconductor chip with the bonding adhesive layer to an electrode of another semiconductor chip or a wiring circuit board,
wherein the semiconductor wafer and the stacked body have a circular shape in plan view, and
in plan view, a diameter A of the semiconductor wafer and a diameter X of the stacked body satisfy a relationship of Expression (1) described below:
A – 1.5 < X < A mm ... (1).
Claim 1 is therefore rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 is rejected under 35 U.S.C. 112(b) at least for its dependency on claim 1.
Claim 3 has a preamble which recites “An adhesive film for semiconductor wafer processing, comprising” then later in the claim provides limitations to the properties of the semiconductor wafer including “the semiconductor wafer and . . . have a circular shape in plan view” and “a diameter A of the semiconductor wafer and a diameter X of the stacked body satisfy a relationship of Expression (1) described below: A – 1.5 < X < A mm ... (1)”. The presence of the claim limitations to the semiconductor wafer are unclear since the claim is, according to the preamble, drawn only to the adhesive film and not the entire structure. It is therefore not clear if one is infringing on the claim when they make the adhesive film having the claimed properties or when they make the entire structure including both the adhesive film and the semiconductor wafer with the claimed properties. Claim 3 is therefore rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For the purposes of this examination, the preamble will be interpreted to read as “A semiconductor structure including a semiconductor wafer and an [[An]] adhesive film for semiconductor wafer processing, the adhesive film comprising”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2007/0141330 A1; Morishima et al.; 06/2007; (“Morishima”) in view of JP 2008-300521 A; Kizaki et al.; 12/2008; (“Kizaki”).
Regarding claim 1. Morishima discloses A method for manufacturing a semiconductor device (Figure 1, [0010], wafer processing using wafer processing tape), comprising:
preparing a semiconductor wafer including a plurality of electrodes on a first side of the semiconductor wafer to stick a stacked body (Figure 1a, wafer circuit substrate #5 including electrodes #4 on a first side has a stacked body #1-#3, sticked thereon), which includes a backgrind tape including a base material (#1, Figure 1, substrate film) and a pressure-sensitive adhesive layer formed on the base material (#2, Figure 1, removable adhesive layer which is at least partially bonded through compression according to [0007] formed on #1), and a bonding adhesive layer formed on the pressure-sensitive adhesive layer (#3, Figure 1, adhesive layer formed on #2), onto the semiconductor wafer on [[a]] the first side in which the electrodes are provided (Figure 1, #1-#3 is formed on the side of #5 where #4s are present);
grinding the semiconductor wafer on a second side opposite to the side in which the electrodes are provided to make the semiconductor wafer [[thin]] thinner (Figure 1C, [0061], opposite side of #5 from #4s is ground down to a depth shown by the presence of the dotted line to become thinner;
dicing the thinned semiconductor wafer and the bonding adhesive layer to be singulated into a semiconductor chip with the bonding adhesive layer (Figures 1d-1e, the thinned structure is singulated into an individual chip with #3 still attached); and
electrically connecting an electrode of the electrodes of the semiconductor chip with the bonding adhesive layer to an electrode of another semiconductor chip or a wiring circuit board ([0002]-[0007], the purpose of the invention is for flip chip packaging in which the singulated chip is part of a larger package whereby the electrodes are connected to a larger package, see [0034] which utilizes the retained adhesive on the chip as part of a subsequent die-bonding step),
wherein the semiconductor wafer and the stacked body have a circular shape in plan view (Figure 1b, the wafer and the stacked body have a circular shape in the plan view).
Morishima does not disclose that in plan view, a diameter A of the semiconductor wafer and a diameter X of the stacked body satisfy a relationship of Expression (1) described below:
A – 1.5 < X < A mm ... (1).
However, Kizaki teaches on pages 4, 7, and 10 that an adhesive film may be formed on a wafer such that the adhesive film has a diameter which is 1 mm smaller than the diameter of the wafer it is placed on (i.e. X=A – 1 mm which is within the claimed range).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the tape structure of Morishima to have a diameter of less than 1.5 mm smaller than a diameter of the wafer, such as the 1 mm smaller considered by Kizaki since doing so is practical technique to ensure complete adhesion to the wafer by the tape without a risk of the edges of the tape extending over the side of the wafer due to slight error in film placement and coming into unintentional contact and/or sticking to other elements (see pages 3-4, 7, and 10 of Kizaki).
Regarding claim 2. Morishima in view of Kizaki discloses The method for manufacturing a semiconductor device according to claim 1,
wherein a bonding adhesive force between the pressure-sensitive adhesive layer (Morishima, #2, Figure 1e) and the bonding adhesive layer (Morishima, #3, Figure 1e) is lower than a bonding adhesive force between the bonding adhesive layer (Morishima, #3, Figure 1e) and the semiconductor wafer (Morishima, #5, Figure 1e) (Figure 1e, [0061], during a pick up process #2 and #3 separate while #3 and #5 remain adhered such that the force between #2 and #3 is lower than the force between #5 and #3).
Regarding claim 3. Morishima discloses A semiconductor structure including a semiconductor wafer and an [[An]] adhesive film for semiconductor wafer processing (Figure 1, [0010], wafer processing using wafer processing tape), the adhesive film comprising
a stacked body (Figure 1a, stacked body #1-#3), which includes a backgrind tape including a base material (#1, Figure 1, substrate film) and a pressure- sensitive adhesive layer formed on the base material (#2, Figure 1, removable adhesive layer which is at least partially bonded through compression according to [0007] formed on #1), and a bonding adhesive layer formed on the pressure-sensitive adhesive layer (#3, Figure 1, adhesive layer formed on #2),
wherein the semiconductor wafer and the stacked body have a circular shape in plan view (Figure 1b, the wafer and the stacked body have a circular shape in the plan view).
Morishima does not disclose that in plan view, a diameter A of the semiconductor wafer and a diameter X of the stacked body satisfy a relationship of Expression (1) described below:
A – 1.5 < X < A mm ... (1).
However, Kizaki teaches on pages 4, 7, and 10 that an adhesive film may be formed on a wafer such that the adhesive film has a diameter which is 1 mm smaller than the diameter of the wafer it is placed on (i.e. X=A – 1 mm which is within the claimed range).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the tape structure of Morishima to have a diameter of less than 1.5 mm smaller than a diameter of the wafer, such as the 1 mm smaller considered by Kizaki since doing so is practical technique to ensure complete adhesion to the wafer by the tape without a risk of the edges of the tape extending over the side of the wafer due to slight error in film placement and coming into unintentional contact and/or sticking to other elements (see pages 3-4, 7, and 10 of Kizaki).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2013/0089970 A1; Amada, Haruo; 04/2013 – [0110] teaches that the tape having a diameter smaller than the diameter of the wafer, “narrow-width peeling tape system” is advantageous for facilitating control of the tape peeling process.
US 2002/0016135 A1; Iwasaki et al.; 02/2002 – [0008] teaches that the tape having a diameter larger than the diameter of the wafer results in unwanted pooling of liquid at the wafer edges during thinning while [0051]-[0052] suggests a diameter smaller than the wafer by 3 mm or less to prevent the pooling at the edges and slowing down the grinding speed to reduce vibration at the edges.
JP 2007-300081 A; Fujii, Shinjiro; 11/2007 – Page 4 teaches that when the outer diameter of the adhesive film is equal to or greater than the diameter of the wafer, there is a higher likelihood of the film adhering to the devices and causing contamination while also increasing the changes of unwanted early peeling. For this reason it is preferable to set the adhesive diameter to be 1-4 mm smaller than the wafer to suppress contamination (page 7).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE KIM can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TYLER J WIEGAND/Examiner, Art Unit 2812
Prosecution Insights