Prosecution Insights
Last updated: July 17, 2026
Application No. 18/858,330

MEMBER FOR SEMICONDUCTOR DEVICE PRODUCTION, AND METHOD FOR PRODUCING SAME

Non-Final OA §102
Filed
Oct 21, 2024
Priority
Dec 27, 2022 — JP 2022-209979 +1 more
Examiner
BURNS, TREMESHA WILLIS
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
RESONAC Corporation
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
673 granted / 867 resolved
+9.6% vs TC avg
Strong +18% interview lift
Without
With
+17.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
54 currently pending
Career history
887
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
47.2%
+7.2% vs TC avg
§102
49.9%
+9.9% vs TC avg
§112
1.8%
-38.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 867 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 – 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Toba et al. (JP 2019-029452). Regarding claim 1, in Figures 1 – 2, Toba discloses a method for producing a member for semiconductor device production, the method comprising:(a) forming a recess (1a) on a surface of an insulating material layer (1);(b) forming a first electroless Ni plating layer (5) on the surface of the insulating material layer and an inner surface of the recess by electroless nickel plating (pg. 5, last paragraph);(c) forming a Cu plating layer (7) on the first electroless Ni plating layer;(d) forming a wiring layer (8) including the Cu plating layer in the recess by removing the Cu plating layer and the first electroless Ni plating layer formed on the surface of the insulating material layer (pg. 6, 6th and 7th paragraphs); and(e) forming a second electroless Ni plating layer (9) on an exposed surface of the wiring layer by electroless nickel plating (pg. 7, 4th paragraph), wherein the first electroless Ni plating layer contains nickel and boron, and a boron content of the first electroless Ni plating layer is 0.3 to 1.0 mass% based on a mass of the first electroless Ni plating layer (pg. 5, last paragraph to pg. 6, 1st paragraph). Regarding claim 2, Toba discloses wherein the second electroless Ni plating layer contains nickel and phosphorus, and a phosphorus content of the second electroless Ni plating layer is 1 to 13 mass% based on a mass of the second electroless Ni plating layer (pg. 7, 4th and 5th paragraphs). Regarding claim 3, Toba discloses wherein the first electroless Ni plating layer formed in step (b) satisfies the following condition:0.3 Ta/T 1.0 where Ta represents a thickness of the first electroless Ni plating layer formed on the inner surface of the recess, and T represents a thickness of the first electroless Ni plating layer formed on the surface of the insulating material layer (pg. 5, last paragraph). Regarding claim 4, Toba discloses wherein step (a) includes:(al) curing a first insulating layer by exposing the first insulating layer formed of a negative photosensitive resin composition;(a2) forming a second insulating layer formed of a negative photosensitive resin composition on a surface of the first insulating layer after curing;(a3) exposing a region of the second insulating layer where the recess is to be formed; and(a4) forming the recess by developing the second insulating layer after exposure (pgs. 3 - 4). Regarding claim 5, in Figures 1 – 2, Toba discloses a member for semiconductor device production comprising: an insulating material layer (1); a recess (1a) formed on a surface of the insulating material layer; a first electroless Ni plating layer (5) formed to cover an inner surface of the recess; a Cu plating layer (7) formed on a surface of the first electroless Ni plating layer and with which the recess is filled (Fig. 2(a)); and a second electroless Ni plating layer formed to cover an exposed surface of the Cu plating layer (Fig. 2(c)), wherein the first electroless Ni plating layer contains nickel and boron, and a boron content of the first electroless Ni plating layer is 0.3 to 1.0 mass% based on a mass of the first electroless Ni plating layer (pg. 5, last paragraph to pg. 6, 1st paragraph). Regarding claim 6, Toba discloses wherein the second electroless Ni plating layer contains nickel and phosphorus, and a phosphorus content of the second electroless Ni plating layer is 1 to 13 mass% based on a mass of the second electroless Ni plating layer (pg. 7, 4th and 5th paragraphs). Regarding claim 7, Toba discloses wherein the recess is a groove having an opening width of 0.5 to 3 µm (pg. 4, 1st paragraph). Regarding claim 8, Toba discloses wherein a thickness of the insulating material layer is less than or equal to 10 µm (pg. 3). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TREMESHA W. BURNS Primary Examiner Art Unit 2847 /TREMESHA W BURNS/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Oct 21, 2024
Application Filed
Jun 24, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
95%
With Interview (+17.7%)
2y 6m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 867 resolved cases by this examiner. Grant probability derived from career allowance rate.

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