DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The preliminary amendment, filed 10/26/2024, has been entered.
Claims 1-15 are pending.
Claims 3 and 5-14 are amended.
Claims 16-26 are cancelled.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01/16/2025, have been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
LAMINATE MANUFACTURING METHOD, INSULATION MATERIAL CONTAINING INORGANIC OXIDE PARTICLES, AND LAMINATE
Claim Objections
Claims 3, 4, 5 and 15 are objected to because of the following informalities:
Claim 3, line 2 currently reads “the second insulation material,” and should be amended to read “a second insulation material” in order to maintain proper antecedent basis. Claims 4, 5, and 15 should be amended accordingly for the same deficiency.
Claim 15, line 9 should be amended to read "electrode is bonded to a connection terminal of the second wiring electrode."
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, it is unclear and indefinite what the applicant intends by the claim limitation “substantially no inorganic oxide particles.” Paragraph 0006 of the specification of the instant application defines the phrase to “include a case where an extremely small amount of inorganic oxide is contained in the second insulation layer,” but does not limit it thereto. Further limits of the amount of inorganic oxide particles in the second insulation layer range up to 20% of the content of the inorganic oxide particles found in the first insulation material, which can range up to 70% by volume, leading to 14% by volume of oxide particles in the second insulation material, thus rendering the term “substantially no inorganic oxide particles” indefinite. For the purposes of examination, it will be interpreted that any amount of oxide particles, from 0% (as disclosed by a content of 5% by volume or less, paragraph 0008) to 14% (discussed above, paragraph 0007) will read on “substantially no inorganic oxide particles.”
The examiner recommends, for clarity of the claims, that the limitation be removed as it is otherwise included in dependent claim 4, or that the options of claim 1 “wherein the second insulation layer includes substantially no inorganic oxide particles” and “wherein the second insulation layer includes second inorganic oxide particles in a content smaller than that of the first inorganic oxide particles included in the first insulation layer” be more clearly separated, and the claims which are intended to depend from each separate limitation (i.e. claims 2 and 3 appear to depend from the second limitation option, and claim 4 appears to depend from the first limitation option) are written more clearly to indicate their intended dependency.
Claims 2-15 are rejected as inheriting the deficiency of claim 1.
Regarding claim 4, it is unclear and indefinite what the applicant intends by the claim limitation “substantially no inorganic oxide particles.” Paragraph 0006 of the specification of the instant application defines the phrase to “include a case where an extremely small amount of inorganic oxide is contained in the second insulation layer,” but does not limit it thereto. Further limits of the amount of inorganic oxide particles in the second insulation layer range up to 20% of the content of the inorganic oxide particles found in the first insulation material, which can range up to 70% by volume, leading to 14% by volume of oxide particles in the second insulation material, thus rendering the term “substantially no inorganic oxide particles” indefinite. For the purposes of examination, it will be interpreted that any amount of oxide particles, from 0% (as disclosed by a content of 5% by volume or less, paragraph 0008) to 14% (discussed above, paragraph 0007) will read on “substantially no inorganic oxide particles.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 7-15 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (US PGPub 2024/0339368; herein known as Nakamura) in view of Dias (US PGPub 2003/0203536; herein known as Dias).
Regarding claim 1, Nakamura teaches (Fig. 4B) a method for manufacturing a stack, comprising: forming a first insulation layer (42, [0341]) on a first support substrate (B, [0333]), the first insulation layer including a first thermosetting resin ([0341]) and first inorganic oxide particles ([0289]); a second insulation layer (41, [0333]) including a second thermosetting resin ([0333]), and bonding a first surface (bottom) of the first insulation layer (42) to a second surface (top) of a second insulation layer (41, [0333]).
Nakamura does not explicitly teach including wherein the second insulation layer includes substantially no inorganic oxide particles or includes second inorganic oxide particles in a content smaller than that of the first inorganic oxide particles included in the first insulation layer.
In analogous art, Dias teaches wherein the second insulation layer (155, [0033]) includes substantially no inorganic oxide particles.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Nakamura and of Dias to include wherein the second insulation layer includes substantially no inorganic oxide particles, in order to reduce flow failure during processing due to filler in the insulating material (Dias, [0006]).
Regarding claim 2, Nakamura in view of Dias teaches the method for manufacturing a stack according to claim 1, wherein a content of the second inorganic oxide particles in a second insulation material forming the second insulation layer is one fifth or less of a content of the first inorganic oxide particles included in a first insulation material forming the first insulation layer. Dias teaches wherein the second insulation layer includes no inorganic oxide particles, which is less than 20% a content of the first inorganic oxide particles.
Regarding claim 3, Nakamura in view of Dias teaches the method for manufacturing a stack according to claim 1, wherein the content of the second inorganic oxide particles in the second insulation material forming the second insulation layer is 5% by volume or less. Dias teaches wherein the second insulation layer includes no inorganic oxide particles, which is less than 5% by volume.
Regarding claim 4, Nakamura in view of Dias teaches the method for manufacturing a stack according to claim 1, wherein the second insulation material forming the second insulation layer includes substantially no inorganic oxide particles (Dias, [0033]).
Regarding claim 5, Nakamura in view of Dias teaches the method for manufacturing a stack according to claim 1, wherein the first insulation material including the first thermosetting resin and the first inorganic oxide particles is adjusted to have a thermal expansion coefficient smaller than that of the second insulation material forming the second insulation layer. Nakamura teaches wherein inclusion of inorganic oxide filler particles is completed in order to tune the CTE of the insulating resin material (Dias, [0033]).
Regarding claim 7, Nakamura in view of Dias teaches (Figs. 4A-4B) the method for manufacturing a stack according to claim 1, wherein the content of the first inorganic oxide particles in the first insulation material including the first thermosetting resin and the first inorganic oxide particles is 15% by volume to 70% by volume ([0302]).
Regarding claim 8, Nakamura in view of Dias teaches (Figs. 4A-4B) the method for manufacturing a stack according to claim 1, further comprising: planarizing ([0251]) the first surface (top) of the first insulation layer (42, [0341]), wherein, in the planarizing the first insulation layer, the first insulation layer is polished such that the arithmetic average roughness of the first surface is 50 nm or less ([0261]).
Regarding claim 9, Nakamura in view of Dias teaches the method for manufacturing a stack according to claim 1, wherein the first support substrate (B, [0340]) includes an inorganic interposer (2y, [0340]) made of an inorganic material ([0235]).
Regarding claim 10, Nakamura in view of Dias teaches (Figs. 4A-4B) the method for manufacturing a stack according to claim 1, wherein a semiconductor chip (1, [0005]) is attached to a surface (bottom) of the second insulation layer (41, [0005]) on a side opposite to the second surface (top).
Regarding claim 11, Nakamura in view of Dias teaches (Figs. 4A-4B) the method for manufacturing a stack according to claim 1, further comprising: planarizing ([0251]) the first surface of the first insulation layer (42, [0341]); forming the second insulation layer (41, [0251]) including the second thermosetting resin on a second support substrate (A, [0333]); and planarizing the second surface ([0341]) of the second insulation layer, wherein, in the bonding, the planarized first surface is bonded to the planarized second surface ([0346]).
Regarding claim 12, Nakamura in view of Dias teaches (Figs. 4A-4B) the method for manufacturing a stack according to claim 1, further comprising: irradiating the second surface (bottom) of the second insulation layer (41) with ultraviolet rays ([0206]).
Regarding claim 13, Nakamura in view of Dias teaches (Figs. 4A-4B) the method for manufacturing a stack according to claim 1, wherein, in the bonding the first surface to the second surface, the first insulation layer and the second insulation layer are bonded to each other by heating them at 250°C or lower ([0206]).
Regarding claim 14, Nakamura in view of Dias teaches (Figs. 4A-4B) the method for manufacturing a stack according to claim 1, further comprising: forming a first wiring electrode (32, [0340]) on the first support substrate (B, [0331]), wherein, in the forming the first insulation layer, the first wiring electrode is encapsulated with the first insulation material (51, [0341]) including the first thermosetting resin and the first inorganic oxide particles (see Figure).
Regarding claim 15, Nakamura in view of Dias teaches (Figs. 4A-4B) the method for manufacturing a stack according to claim 14, further comprising: forming a second wiring electrode (31, [0340]) on the second support substrate (A, [0333]); and forming the second insulation layer (41, [0333]) on the second support substrate to encapsulate the second wiring electrode with the second insulation material including the second thermosetting resin, wherein, in the bonding, when the first surface of the first insulation layer is bonded to the second surface of the second insulation layer, a connection terminal of the first wiring electrode is bonded to a connection terminal of the second wiring electrode ([0347]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura in view of Dias as applied to claim 1 above, and further in view of Liff et al. (US PGPub 2021/0098411; herein known as Liff).
Regarding claim 6, Nakamura in view of Dias teaches the method for manufacturing a stack according to claim 1, but does not explicitly teach wherein the first insulation material including the first thermosetting resin and the first inorganic oxide particles is adjusted to have a thermal expansion coefficient of 40 x 10-6/K or less.
In analogous art, Liff teaches wherein the first insulation material (107, [0029]) including the first thermosetting resin (106, [0028]) and the first inorganic oxide particles (108, [0029]) is adjusted to have a thermal expansion coefficient of 40 x 10-6/K or less ([0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Nakamura in view of Dias and of Liff to include wherein the first insulation material including the first thermosetting resin and the first inorganic oxide particles is adjusted to have a thermal expansion coefficient of 40 x 10-6/K or less in order to reduce in-plane CTE mismatch between the insulation material and other parts of the stack and therefore enable smaller conductive interconnect bonding layer pitch, aiding in miniaturization of the device (Liff, [0029]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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