DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 2 and 9 are objected to because of the following informalities:
The subject “the first and second command/address interfaces” in claim 2, lines 1-2 does not have a verb.
The term “shared data strobe interface” in claim 9, line 2 should be “the shared data strobe interface”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8, 10 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation "the active edges" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation "the shared strobe signaling interface" in lines 7-8. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 recites the limitation “the first data strobe signal strobe signaling interface” in line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim 21 recites “means for enabling the first write data burst to be sampled within the first data interface at times indicated by the first data strobe signal, and for enabling the second write data burst to be sampled within the second data interface at times indicated by the first data strobe signal.” in lines 9-12.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 11, 13 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Partsch (WO 2020176446 A1).in view of Ware et al. (US 2026/0212905, hereinafter “Ware”).
Regarding claims 1, 11 and 21, Partsch discloses an integrated-circuit memory component and a method comprising:
a data interface (Abstract and claim 1, line 13);
a command/address interface to receive respective first and second memory access commands (WR1 and WR2, [0017] Referring now to the boosted-bandwidth waveforms shown at 151, write command/address values WR1 and WR2 are transmitted from the control component to the memory component in successive system clock cycles, followed by respective continuously- clocked data bursts at 161 and 163— that is, data bursts transmitted synchronously with a free- running write data clock), the first memory access command indicating that a first write data burst is to be received via the data interface and the second memory access command indicating that a second write data burst is to be received via the data interface;
a shared data strobe interface to receive a first data strobe signal; and
control circuitry to:
enable the first write data burst to be sampled within the first data interface at times indicated by the first data strobe signal, and
enable the second write data burst to be sampled within the second data interface at times indicated by the first data strobe signal (The data interface samples first write data corresponding to the first command/address value at times indicated by toggling of the data strobe, and samples second write data corresponding to the second command/address value at times indicated by toggling of the data clock).
Partsch does not use two data interfaces and two command/address interfaces. However, Ware discloses the use first and second data interfaces and first and second command/address interfaces to output and receive data signals associated with a second set of memory banks (claim 22) and to output command/address signals directed to a second set of memory banks (claim 31).
It would have been obvious to one having ordinary skill in the art to use first and second data interfaces and first and second command/address interfaces to o output and receive data signals and output command/address signals in a memory device.
Regarding claims 3 and 13, Ware discloses the integrated-circuit memory component of claim 1 wherein first and second command/address interfaces and first and second data interfaces are disposed on a first integrated circuit die that forms at least part of the integrated-circuit memory component (claims 21 and 22, the control IC is on a die (paragraph [0014] and paragraph [0045], lines 22-24)).
Allowable Subject Matter
Claims 2, 4-7, 9, 10, 12, 14-18 and 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the first and second command/address interfaces to receive the respective first and second memory access commands at respective times that are offset from one another by a first interval and wherein the control circuitry to enable the first and second write data bursts to be sampled within the first and second data interfaces comprises circuitry to enable the first and second write data bursts to be sampled over respective second and third intervals that are offset from one another by the first interval.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 4, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the control circuitry to enable the first write data burst to be sampled at times indicated by the first data strobe signal comprises circuitry to (i) generate a first delayed data strobe signal having a first calibrated phase offset from the first data strobe signal and (ii) enable the first write data burst to be sampled in response to transitions of the first delayed data strobe signal.” in combination with the other limitations thereof as is recited in the claim.
Claims 5 and 6 depend on claim 4.
Regarding claim 7, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the first data strobe signal comprises a plurality of active transitions that are preceded by a strobe preamble and succeeded by a strobe postamble, the active transitions continuing throughout an interval that exceeds a duration of the first write data burst and exceeds a duration of the second write data burst.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 9, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the first command/address interface, the first data interface and shared data strobe interface are implemented in a first integrated circuit die within the integrated-circuit memory component and the second command/address interface and the second data interface are implemented in a second integrated circuit die within the integrated-circuit memory component and wherein the control circuitry to enable the second write data burst to be sampled within the second data interface at times indicated by the first data strobe signal comprises circuitry to convey the first data strobe signal from the first integrated circuit die to the second integrated circuit die.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 10, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the first and second command/address interfaces comprise circuitry to receive respective third and fourth memory access commands, the third memory access command indicating that a first read data burst is to be transmitted to a memory control component via the first data interface and the fourth memory access command indicating that a second read data burst is to be transmitted to the memory control component via the second data interface, and wherein the control circuitry comprises circuitry to transmit a second data strobe signal via the shared strobe signaling interface to indicate times at which the memory control component is to sample the first and second read data bursts.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 12, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein receiving the first and second memory access commands via the first and second command/address interfaces comprises receiving the first and second memory access commands at respective times that are offset from one another by a first interval and wherein sampling the first and second write data bursts within the first and second data interfaces comprises sampling the first and second write data bursts over respective second and third intervals that are offset from one another by the first interval.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 14, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein sampling the first write data burst at times indicated by the first data strobe signal comprises generating a first delayed data strobe signal having a first calibrated phase offset from the first data strobe signal and sampling the first write data burst in response to transitions of the first delayed data strobe signal.” in combination with the other limitations thereof as is recited in the claim. Claims 15 and 16 depend on claim 14.
Regarding claim 17, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the first data strobe signal comprises a plurality of active transitions that are preceded by a strobe preamble and succeeded by a strobe postamble, the active transitions continuing throughout an interval that exceeds a duration of the first write data burst and exceeds a duration of the second write data burst.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 18, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the first data strobe signal comprises active transitions that are preceded by a strobe preamble and succeeded by a strobe postamble, and wherein a first subset of the active edges indicates times at which an initial portion of first write data burst is to be sampled and a second subset of the active edges indicates times at which a trailing portion of the second write data burst is to be sampled, the first subset including at least one active edge not included in the second subset and vice-versa.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 20, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “:receiving third and fourth memory access commands via the first and second command/address interfaces, respectively, the third memory access command indicating that a first read data burst is to be transmitted to a memory control component via the first data interface and the fourth memory access command indicating that a second read data burst is to be transmitted to the memory control component via the second data interface; and transmitting a second data strobe signal via the shared strobe signaling interface to indicate times at which the memory control component is to sample the first and second read data bursts.” in combination with the other limitations thereof as is recited in the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUAN HOANG whose telephone number is (571)272-1779. The examiner can normally be reached 7:30AM-4:00PM M-F.
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/HUAN HOANG/Primary Examiner, Art Unit 2827
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