Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 4 is objected to because of the following informalities:
Regarding claim 4: Examiner believes that Applicants intentions are to specify the one or more column select lines that are to be selected. Hence, Examiner suggests amending the claims as follows:
Claim 4: The 3D memory device of claim 1, further comprising:
one or more column address buses to provide a column address to the column address decoder specifying the one or more of the plurality of column select lines to be the selected column select lines; and
wherein the two or more global data signal buses and the one or more column address buses are shared between a column of mats in a block of the 3D memory device.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1: Because the claim states “a plurality of column select lines to select
a column of memory cells of a memory cell array” then one of ordinary skill in the art expects the column select lines to select a column within the memory cell array from among the columns of the memory cell array BUT the term “column select lines” was used in a different sense within the disclosure, wherein column select lines are not disclosed to select a column of memory cells within a memory cell array but rather are disclosed to select one or more sense amplifiers (see [0029]), wherein each sese amplifier corresponds to a memory cell array that it is under (see FIG. 2B), such that values of memory cells along an active word line in each memory cell array corresponding to the one or more selected sense amplifiers are read out in a read operation. Hence, the term column in Applicant’s term “column select lines” (see 504 in FIG. 5) seems to be NOT directed to a column of memory cells within a memory cell array but rather a column within an array of mats (see FIG. 3).
Hence, the claim comprises subject matter that was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
One way to fix the claim is to amend the claim as follows:
Claim 1: A 3D memory device comprising:
a plurality of mats, each mat of the plurality of mats including a memory cell array;
logic circuitry disposed under the memory cell array in each mat, the logic circuitry
including:
a plurality of column select lines to select a sense amplifier a corresponding mat;
a local data signal bus to communicate data to and from the memory cell array of
the corresponding mat;
two or more global data signal buses to communicate data externally to and from
the corresponding mat;
a column address decoder to select one or more of the plurality of column select
lines as one or more selected column select lines of the corresponding mat; and
at least one selectable global array data bus redriver including a data bus selector
circuit controllable by a select signal to select one of the two or more global data signal
buses as selected global data signal bus for coupling to the local data signal bus, and a set of amplifiers to amplify data signals communicated between the selected global data signal bus and the local data signal bus.
Claims 2-16 depend on claim 1.
Regarding claim 17: This claim is rejected for reasons similar to those given above in regards to claims 1. Claim 18 depends on claim 17.
Regarding claim 19: This claim is rejected for reasons similar to those given above in regards to claims 1. Claim 20 depends on claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827
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