CTNF 18/871,557 CTNF 88364 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement 1. The information disclosure statements (IDS) submitted and are in compliance with the provisions of 37 CFR 1.97. According, the information disclosure statement is being considered by the Examiner. Examiner Notes 2 . Examiner cites particular paragraphs, columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. Claim Rejections - 35 USC § 103 07-20-aia AIA 3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA 4. Claim s 1, 3-14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kaneoka et al. (US. Pub. 2007/0158560; hereinafter “Kaneoka”) in view of Zingher (US. Pat. 4443278; hereinafter “Zingher”) . Regarding claim 1 , Kaneoka discloses a method for testing a packaging substrate for multi-device in-package integration with at least one electron beam column ( a semiconductor inspection system, in Fig. 1, used in an electrical defect inspection in a process of manufacturing semiconductor devices, electrical defects such as a conducting defect and a short circuit associated with the reduction in size of the structure in the semiconductor device, see paragraphs [0003, 5] ), the method comprising: placing the semiconductor device ( 31 in Fig. 1 ) on a stage ( 33 ) in a vacuum chamber ( 30 ); flooding at least portions of the vacuum chamber with positive ions and/or negative charges ( an ion source 21 of an ion beam column 20 provided a flood ion beam 22 that carried positive charges (positive charge ions) and negative charges (negative charge ions). See Fig. 1 and [0043-44] ); generating an electric field between one or more electrodes and the semiconductor device, the electric field being configured to accelerate the positive ions or the negative charges towards the semiconductor device ( using an electric field of an extractor electrodes 13 and 23 for extracting electrons from an electron beam 12 and extracting ions from an ion beam 22 toward the semiconductor device 31. See [0047] ); and testing the semiconductor device ( 31 ) in the vacuum chamber ( 30 ) with at least one electron beam column ( an electron beam column 10 in Fig. 1) , wherein the flooding of the vacuum chamber with positive ions and/or negative charges is provided by an ion source ( an ion source 21 in Fig. 1 ) at least partially provided in the vacuum chamber ( see Fig. 1 and [0042- 43] ). Kaneoka does not specify about placing a packaging substrate on a stage in a vacuum chamber. Zingher discloses an inspection system (Fig. 9 and 11 and abstract) for testing a package substrate (a multi-layer ceramic (MLC) packaging substrate in Fig. 7, called a specimen under test 18 in Fig. 9 and 36 in Fig. 11) comprising the packaging substrate (18, 36) on a stage (19 in Fig. 9) in a vacuum chamber (20 in Fig. 11). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the inspection system of Kaneoka by placing a packaging substrate on a stage in a vacuum chamber for inspection as taught by Zingher in order to meet the system design and specification requirement. Regarding claim 3 , Kaneoka and Zingher disclose the method of claim 1, Kaneoka further teaches wherein the ion source is selected from the group consisting of: an ion source with a gas supply, a VUV source, a spark generating the positive ion source (see [0043]). Regarding claim 4 , Kaneoka and Zingher disclose the method of claim 1, Kaneoka further teaches wherein the electric field is uniform at a surface of the packaging substrate or wherein the electric field is uniform between the surface of the packaging substrate and the one or more electrodes (see Fig. 1 and [0047]). Regarding claim 5 , Kaneoka and Zingher disclose the method of claim 1, wherein a gap (see Fig. 1 of Kaneoka) is provided between the one or more electrodes (13 and 23 of Kaneoka) and the packaging substrate (the packaging substrate 18 or 36 of in view Figs. 7-9 and 11 of Zingher). Regarding claim 6 , Kaneoka and Zingher disclose the method of claim 1, wherein a gap (see Fig. 1 of Kaneoka) is provided between the at least one electron beam column (10, 20 in Fig. 1 of Kaneoka) and the packaging substrate (the packaging substrate 18 or 36 of in view Figs. 7-9 and 11 of Zingher). Regarding claim 7 , Kaneoka and Zingher disclose the method of claim 1, wherein the testing of the packaging substrate comprises: directing at least one electron beam of the at least one electron beam column on at least a first portion of the packaging substrate; directing the at least one electron beam of the at least one electron beam column on at least a second portion of the packaging substrate; and detecting signal electrons emitted upon impingement of the at least one electron beam for testing a first device-to-device electrical interconnect path of the packaging substrate ( see at least in [0047-50] of Kaneoka; or at least in column 7 lines 36 to column 8 lines 68 of Zingher ). Regarding claim 8 , Kaneoka and Zingher disclose the method of claim 7, Zingher further teaches wherein the at least one electron beam is directed on at least the first portion with a first landing energy and on at least the second portion with a second landing energy different than the first landing energy ( see at least in column 7 lines 36 to column 8 lines 68 of Zingher ). Regarding claim 9 , Kaneoka and Zingher disclose the method of claim 8, Zingher further teaches wherein the signal electrons are detected upon impingement of the at least one electron beam with the second landing energy for reading of a charge on the packaging substrate ( see at least in column 7 lines 36 to column 8 lines 68 of Zingher ). Regarding claim 10 , Kaneoka and Zingher disclose an apparatus for testing a packaging substrate in accordance with the method of claim 1 (see an inspection apparatus in Figs. 9 and 11of Zingher). Regarding claim 11 , Kaneoka discloses an apparatus for contactless testing of a packaging substrate for multidevice in-package integration ( a semiconductor inspection system, in Fig. 1, used in an electrical defect inspection in a process of manufacturing semiconductor devices, electrical defects such as a conducting defect and a short circuit associated with the reduction in size of the structure in the semiconductor device, see paragraphs [0003, 5] ), comprising: a vacuum chamber ( a vacuum chamber 30 in Fig. 1 ); a stage ( a sample stage or semiconductor device stage 33 ) within the vacuum chamber ( 30 ), the stage being configured to support the packaging substrate ( see Fig. 1 ); a charged particle beam column ( an electron beam column 10 ) configured to generate an electron beam ( an electron beam 12 ), the charged particle beam column comprising: an objective lens ( a condenser lens 14 and objective lens 17 ) configured to focus the electron beam on the packaging substrate ( see [0047] ); a scanner configured to scan the electron beam to different positions on the packaging substrate ( “An image generation unit 75 captures a signal of the detector 41 in synchronization with a scanning signal of each beam” in [0042]. “a deposition layer 53 is formed by supplying a deposition gas 52 from the deposition gas source 51 and scanning the electron beam 12 thereon…” in [0050]. Also see [0043-44, 47-48, 51-52] ); and an electron detector ( a detector 41 ) for detecting signal electrons emitted upon impingement of the electron beam on the packaging substrate ( “The SEM column 10 is controlled by a SEM control unit 18, and the ion beam column 20 is controlled by an ion beam column control unit 28. An image generation unit 75 captures a signal of the detector 41 in synchronization with a scanning signal of each beam, and generates an image” see at least in [0042] ); the apparatus further comprising: an ion source ( such as an ion source 21 ) at least partially provided in the vacuum chamber ( see Fig. 1 ) for flooding the vacuum chamber with positive ions and/or negative charges ( an ion source 21 of an ion beam column 20 provided a flood ion beam 22 that carried positive charges (positive charge ions) and negative charges (negative charge ions). See Fig. 1 and [0043-44] ); one or more electrodes configured to generate an electric field between one or more electrodes and the packaging substrate, the electric field being configured to accelerate positive ions or negative charges towards the substrate ( using an electric field of an extractor electrodes 13 and 23 for extracting electrons from an electron beam 12 and extracting ions from an ion beam 22 toward the semiconductor device 31. See [0047] ); and an analysis unit for determining ( 75-76 in Fig. 1 ), based on the signal electrons, if a first device-to-device electrical interconnect path is defective ( An image generation unit 75 captures a signal of the detector 41 in synchronization with a scanning signal of each beam, and generates an image. An image processing unit 76 compares an image generated by the image generation unit 75 in the unit of a cell or a die of the semiconductor manufacturing process, and detects electrical defects, such as a conducting defect and short circuit inside the wafer. See [0042, 47-48] ). Kaneoka does not specify about placing a packaging substrate on a stage in a vacuum chamber. Zingher discloses an inspection system (Fig. 9 and 11 and abstract) for testing a package substrate (a multi-layer ceramic (MLC) packaging substrate in Fig. 7, called a specimen under test 18 in Fig. 9 and 36 in Fig. 11) comprising the packaging substrate (18, 36) on a stage (19 in Fig. 9) in a vacuum chamber (20 in Fig. 11). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the inspection system of Kaneoka by placing a packaging substrate on a stage in a vacuum chamber for inspection as taught by Zingher in order to meet the system design and specification requirement. Regarding claim 12 , Kaneoka and Zingher disclose the apparatus of claim 11, Kaneoka further teaches wherein the one or more electrodes (13), are provided in the charged particle beam column (12)(see Fig. 1). Regarding claim 13 , Kaneoka and Zingher disclose the apparatus of claim 12, Kaneoka further teaches wherein the one or more electrodes (13) are positioned to guide signal electrons towards the detector (41)(see Fig. 1). Regarding claim 14 , Kaneoka and Zingher disclose the apparatus according to claim 11, explicitly specifying that wherein the one or more electrodes are at least one assembly of four or eight electrodes configured to generate a multipole field for guiding signal electrons. However having additional electrodes at specific number such as four or eight electrodes is a known practice in the art and the specifics would simply be a matter of inventor design choice. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the inspection system of Kaneoka and Zingher by having at least one assembly of four or eight electrodes configured to generate a multipole field for guiding signal electrons in order to meet the system design and specification requirement. Regarding claim 17 , Kaneoka and Zingher disclose the apparatus of claim 11, further comprising: a scan controller configured to sequentially direct the electron beam to pairs of first and second surface contact points for testing respective device-to-device electrical interconnect paths extending between the respective pairs of first and second surface contact points ( see at least in [0047-50] of Kaneoka; or at least in column 7 lines 36 to column 8 lines 68 of Zingher ) . 07-21-aia AIA 5. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kaneoka in view of Zingher and further in view of Hiroi et al. (US. Pat. 7122796; hereinafter “Hiroi”) . Regarding claim 15 , Kaneoka and Zingher disclose the apparatus of claim 11, except for explicitly specifying that wherein the stage comprises: a conductive stage surface connected directly or indirectly to ground for providing a reference potential. Hiroi discloses an inspection apparatus includes control of an acceleration voltage of an electron beam, irradiation of the electron beam to an object to be inspected mounted on a stage which is continuously moving at least in one direction, and detection of at least one of secondary electrons and reflected electrons emanated from the object in response to the irradiation ( see Fig. 13 and abstract ) comprising a conductive stage surface ( a wafer holder 21 in Fig. 13 ) connected directly or indirectly to ground for providing a reference potential ( Fig. 13 shows the wafer holder 21 connected to potentials E0-E2 to the ground. See Col. 16 lines 50-68 ). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the inspection system of Kaneoka and Zingher by having a conductive stage surface connected directly or indirectly to ground for providing a reference potential as taught by Hiroi for purpose of enables to detect fine defect in substrate with high reliability and high speed and enables to manufacture reliable semiconductor device. 6. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kaneoka in view of Zingher and further in view of Iwasaki (US. Pub. 2005/0174140 A1; hereinafter “Iwasaki”) . Regarding claim 16 , Kaneoka and Zingher disclose the apparatus of claim 11, except for explicitly specifying wherein the electron detector comprises: an energy filter for the signal electrons. Iwasaki discloses a thin film transistor array inspection system (Fig. 7) comprising the electron detector (a secondary electron detector 6 in Fig. 7) comprises: an energy filter (an energy filter 5) for the signal electrons (see [0054-55). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the inspection system of Kaneoka and Zingher by having the electron detector comprises: an energy filter for the signal electrons as taught by Iwasaki for purpose of enhancing accurate detection of desired reflected electron signals from detection points of the sample under test . 12-57 AIA Prior Art of Record 07-96 AIA 7. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Matsui (U.S Pat. 6700122) discloses a wafer inspection system (see specification for more details). Loi (U.S Pat. 6232787) discloses a microstructure defect detection system (see specification for more details). Nakasuji (U.S Pub. 7095022) discloses an electron beam system (see specification for more details) . Conclusion 8 . Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANG LE whose telephone number is (571)272-9349. The examiner can normally be reached on Monday thru Friday 7:30AM-5:00PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on (571) 272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THANG X LE/Primary Examiner, Art Unit 2858 6/12/2026 Application/Control Number: 18/871,557 Page 2 Art Unit: 2858 Application/Control Number: 18/871,557 Page 3 Art Unit: 2858 Application/Control Number: 18/871,557 Page 4 Art Unit: 2858 Application/Control Number: 18/871,557 Page 5 Art Unit: 2858 Application/Control Number: 18/871,557 Page 6 Art Unit: 2858 Application/Control Number: 18/871,557 Page 7 Art Unit: 2858 Application/Control Number: 18/871,557 Page 8 Art Unit: 2858 Application/Control Number: 18/871,557 Page 9 Art Unit: 2858
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