Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5, 7, 13-14, 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Brueggen (US 2018/0212625).
Regarding claim 1, Brueggen teaches a method comprising: obtaining a codeword generated by a computer operation applied to an original codeword, wherein the original codeword encodes a plurality of symbols (Brueggen, para. [0014], lines 2-7, “a list decoder circuit may include a Berlekamp-Massey algorithm [BMA] circuit to generate a series of error locator polynomials by processing trial decodes in parallel using syndromes corresponding to symbol group erasure iterations of a codeword provided by a plurality of memory devices”); computing, using the codeword, a plurality of syndrome values characterizing a difference between the codeword and the original codeword (Brueggen, para. [0021], lines 1-7, “List decode circuit 100 may receive the codewords and perform error detection and correction for the received codewords. For each received codeword, syndrome calculation circuit 102 may calculate a syndrome. To calculate the syndrome of a codeword, syndrome calculation circuit 102 may compute an expected codeword and compare the expected codeword to the received codeword”); identifying a reduced set of error locator polynomials (ELPs) for the codeword (Brueggen, para. [0030] teaches generating a series of ELPs using trial decodes and the Berlekamp-Massey algorithm; para. [0045] teaches using device status information to forego certain trial decodes and only process trial decodes corresponding to candidate failed devices, which equates to reducing the set of candidate ELPs), wherein each ELP of the reduced set of ELPs is associated with (i) at least one potential error within a respective group of symbols of a plurality of groups of symbols of the codeword (Brueggen, para. [0031], lines 2-4, “A trial erasure decode may be a trial decode in which a symbol group contributed by a memory device to the codeword is erased”; each trial decode generates a corresponding ELP associated with a memory device symbol group) and (ii) absence of potential errors outside the respective group of symbols (Brueggen, para. [0054] teaches the ELP evaluation circuit evaluating whether a resulting error pattern contains errors in a “soft” failed memory device and no errors anywhere else); selecting, in view of the plurality of syndrome values, an indicator ELP from the reduced set of ELPs (Brueggen, para. [0041], lines 18-20, “The ELP resulting from the non-trial erasure decode may be passed to MUX circuit 210, which may provide the ELP to an ELP evaluation circuit”; para. [0062], lines 7-10, “the ELP generated from the trial non-erasure decode may be immediately selected by the MUX circuit and passed to the ELP evaluation circuit”), wherein the indicator ELP is associated with a corrupted group of symbols of the plurality of groups of symbols (Brueggen, para. [0054] teaches the ELPs associated with trial decodes for respective memory device symbol groups and determining whether the errors are confined to a particular “soft” failed memory device), the corrupted group of symbols having at least one error (Brueggen, para. [0054], lines 5-10, “The ELP evaluation circuit may evaluate the ELP to determine if the resulting error pattern has errors in the data from the ‘soft’ failed memory device and no errors anywhere else. If so, it is considered very likely to be the actual error pattern and the BMA circuit may terminate the other trial decodes”); and identifying, using the indicator ELP, the corrupted group of symbols (Brueggen, para. [0054] teaches evaluating the selected ELP to determine that errors are present in the “soft” failed memory device and nowhere else, and terminating the remaining trial decodes once the determination is made).
Brueggen fails to explicitly teach a “reduced set” of ELPs or an “indicator ELP” as recited in the claim. However, Brueggen teaches generating multiple ELPs corresponding to trial decodes associated with respective memory-device symbol groups, selectively limiting the trial decodes performed based on memory device status information, selecting a generated ELP for evaluation, and determining whether the selected ELP corresponds to the likely actual error pattern associated with a particular memory device symbol group.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Brueggen’s teachings of limiting the consideration of ELPs associated with candidate failed devices results in a reduced set of candidate ELPs and that the selected ELP acts as an indicator of the memory device symbol group associated with the detected errors, to include the limitations of “reduced set” of ELPs or an “indicator ELP”.
The suggestion/motivation for doing so would be to improve decoding efficiency.
Regarding claim 2, Brueggen teaches the method of claim 1, wherein the computer operation comprises storing the original codeword in a memory system and reading the codeword from the memory system (Brueggen, para. [0019], lines 1-2, “In some implementations, list decode circuit 100 may be part of a larger memory controller system”; para. [0020], lines 1-3, “The memory controller system may read information from a group of memory devices included in the computing system”).
Regarding claim 3, Brueggen teaches the method of claim 2, wherein each group of symbols of the plurality of groups of symbols is stored in a respective memory device of a plurality of memory devices of the memory system (Brueggen, para. [0020], lines 3-7, “Information may be read out of the memory devices one error-correction-encoded word [referred to herein as a codeword] at a time. For a read operation, each memory device in the group may contribute a group of symbols to the codeword”).
Regarding claim 5, Brueggen teaches the method of claim 4, further comprising: retrieving an additional codeword stored in the memory system; and responsive to identifying that the given memory device is a failed memory device, treating each symbol of the additional codeword stored in the given memory device as an erasure during error correction of the additional codeword (Brueggen, para. [0045], lines 13-18, “in response to determining that a memory device among the plurality of memory devices contributing symbols to the codeword is known to be firm failed, BMA circuit 308 may initiate a trial non-erasure decode for the codeword and a trial erasure decode in which the symbol group contributed by the failed memory device is erased”). Brueggen does not explicitly teach an additional codeword, however it does teach decoding a codeword after determining that a memory device has failed and treating symbols that correspond to the failed memory device as erasures during decoding. One of ordinary skill in the art would have understood that the same failed device handling would be applied to subsequent processing of codewords because the failed status of the memory device would still be necessary information for later decoding operations.
Regarding claim 7, Brueggen teaches the method of claim 1, wherein each ELP of the reduced set of ELPs is agnostic about a number of potential errors within the respective group of symbols of the plurality of groups of symbols (Brueggen, para. [0054], lines 5-10, “The ELP evaluation circuit may evaluate the ELP to determine if the resulting error pattern has errors in the data from the ‘soft’ failed memory device and no errors anywhere else. If so, it is considered very likely to be the actual error pattern and the BMA circuit may terminate the other trial decodes”).
Claim 13 is a system with limitations similar to the method of claim 1, and is rejected under the same rationale.
Claim 14 is a system with limitations similar to the methods of claim 1 and claim 3, and is rejected under the same rationale.
Claim 16 is a system with limitations similar to the method of claim 5, and is rejected under the same rationale.
Claim 19 is a system with limitations similar to the method of claim 7, and is rejected under the same rationale.
Claims 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Brueggen, in view of Richter et al. (US 12,298,849), hereinafter Richter.
Regarding claim 4, Brueggen teaches the method of claim 3, further comprising: determining, using the indicator ELP, that each symbol of the corrupted group of symbols has an error (Brueggen, para. [0054], lines 5-10, “The ELP evaluation circuit may evaluate the ELP to determine if the resulting error pattern has errors in the data from the ‘soft’ failed memory device and no errors anywhere else. If so, it is considered very likely to be the actual error pattern and the BMA circuit may terminate the other trial decodes”); and responsive to identifying that the corrupted group of symbols is stored in a given memory device of the plurality of memory devices (Brueggen, para. [0031], lines 2-4, “A trial erasure decode may be a trial decode in which a symbol group contributed by a memory device to the codeword is erased”; each trial decode generates a corresponding ELP associated with a memory device symbol group).
Brueggen fails to teach increasing a fail counter for the given memory device; and responsive to the fail counter reaching a threshold value, identifying the given memory device as a failed memory device.
However, Richter, in an analogous art, teaches increasing a fail counter for the given memory device (Richter, col. 23, lines 15-18, “When retrieving data from a portion of memory, an error counter 410 may detect and count the quantity of errors in the data. The count may be incremented with each error detected”); and responsive to the fail counter reaching a threshold value (Richter, Fig. 5, step 515, “Max Error Count Satisfied?”), identifying the given memory device as a failed memory device (Richter, Fig. 5, steps 520, 525, & 535).
Brueggen and Richter are both considered to be analogous to the claimed invention because both are in the same field of error management in memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Brueggen to incorporate the teachings of Richter by including the functionality of having error count monitoring and determining device failure when an error threshold is reached.
The suggestion/motivation for doing so would be to identify consistently unreliable memory devices and improve memory system reliability by removing devices that have excessive error conditions.
Claim 15 is a system with limitations similar to the method of claim 4, and is rejected under the same rationale.
Claims 6, 11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Brueggen, in view of Stanisavljevic et al. (US 2021/0288669), hereinafter Stanisavljevic.
Regarding claim 6, Brueggen teaches the method of claim 1, but fails to teach wherein the plurality of symbols of the original codeword comprises a number of error correction (EC) symbols, and wherein the number of EC symbols is less than twice a number of symbols in each group of symbols of the plurality of groups of symbols.
However, Stanisavljevic, in an analogous art, teaches wherein the plurality of symbols of the original codeword comprises a number of error correction (EC) symbols, and wherein the number of EC symbols is less than twice a number of symbols in each group of symbols of the plurality of groups of symbols (Stanisavljevic, para. [0024], lines 14-16, “Typically the RS decoder can detect 2t symbol errors and can correct up to "t" symbols in a codeword that contain errors where 2t equals the number of parity symbols (i.e., N-k)”).
Brueggen and Stanisavljevic are both considered to be analogous to the claimed invention because both are in the same field of error management in memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Brueggen to incorporate the teachings of Stanisavljevic by including the functionality of selecting the number of error correction symbols according to a number of parity symbols.
The suggestion/motivation for doing so would be to allow for the desired error correction capability.
Regarding claim 11, Brueggen teaches the method of claim 1, but fails to teach further comprising: obtaining, using the indicator ELP, an error correction polynomial representing the difference between the codeword and the original codeword; and obtaining the original codeword using the codeword and the error correction polynomial.
However, Stanisavljevic teaches further comprising: obtaining, using the indicator ELP, an error correction polynomial representing the difference between the codeword and the original codeword; and obtaining the original codeword using the codeword and the error correction polynomial (Stanisavljevic, para. [0031], lines 22-28, “The error locator polynomial L(x), the error locations "Xi", and the error values or magnitudes "Yi", e.g., the error polynomial e(x), are fed into the Error Corrections block 80 to determine the original code word c(x). At Error correction block 80 the original codeword c(x) is reconstructed from the delayed decoder input r(x) and the computed error polynomial e(x)”).
Brueggen and Stanisavljevic are both considered to be analogous to the claimed invention because both are in the same field of error management in memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Brueggen to incorporate the teachings of Stanisavljevic by including the functionality of generating an error polynomial from identified error locations and magnitudes, and reconstructing the original codeword using the error polynomial.
The suggestion/motivation for doing so would be to improve error correction capability and facilitating correction of corrupted data.
Claim 17 is a system with limitations similar to the method of claim 11, and is rejected under the same rationale.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Brueggen, in view of Feng (US 7,788,570).
Regarding claim 8, Brueggen teaches the method of claim 1, but fails to teach wherein each ELP of the reduced set of ELPs has an order that is equal to a number of symbols in each group of symbols of the plurality of groups of symbols.
However, Feng, in an analogous art, teaches wherein each ELP of the reduced set of ELPs has an order that is equal to a number of symbols in each group of symbols of the plurality of groups of symbols (Feng, col. 5, lines 41-48, “The received codeword comprises a plurality of symbols, the modified RS decoder, is capable of correcting a contiguous burst of corrupted symbols of length LB and the parameter is LB … each of the pre-computed polynomials indicates a number of contiguous error locations, where the number is equal to a value of L. corresponding to the pre-computed polynomial”).
Brueggen and Feng are both considered to be analogous to the claimed invention because both are in the same field of Reed-Solomon error correction techniques.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Brueggen to incorporate the teachings of Feng by including the functionality of using pre-computed error locator polynomials corresponding to contiguous groups of symbol errors.
The suggestion/motivation for doing so would be to allow for efficient identification of error locations.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Brueggen, in view of Kline et al. (US 7,694,207), hereinafter Kline.
Regarding claim 9, Brueggen teaches the method of claim 1, but fails to teach wherein the reduced set of ELPs is a subset of polynomials of an order that is equal to a number of symbols in each group of symbols, and wherein one or more coefficients of the reduced set of ELPs belong to a group of elements consisting of a zero element and a unity element.
However, Kline, in an analogous art, teaches wherein the reduced set of ELPs is a subset of polynomials of an order that is equal to a number of symbols in each group of symbols, and wherein one or more coefficients of the reduced set of ELPs belong to a group of elements consisting of a zero element and a unity element (Kline, col. 4, lines 30, “In the case of F=GF(2), a BCH code…”; col. 4, lines 44-45, “Since the code is binary, the error as a polynomial is…”; col. 5, lines 1-2, “the error-locator polynomial, defined as…”). Kline teaches BCH decoding in GF(2), where the code and corresponding error polynomial are binary, and also te4aches determining coefficients of an error locator polynomial. One of ordinary skill in the art would understand that coefficients of a polynomial over GF(2) are limited to the elements 0 and 1.
Brueggen and Kline are both considered to be analogous to the claimed invention because both are in the same field of error correction techniques utilizing polynomials.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Brueggen to incorporate the teachings of Kline by including the functionality of binary polynomial techniques.
The suggestion/motivation for doing so would be to improve decoding efficiency and reduce hardware complexity.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Brueggen, in view of Elia et al. (US 2013/0326315), hereinafter Elia.
Regarding claim 10, Brueggen teaches the method of claim 1, but fails to teach wherein each symbol of the plurality of symbols is an element of a Galois Field GF(2q) comprising 2q elements, wherein coefficients of each ELP of the reduced set of ELPs belong to a subset of the Galois Field GF(2q), wherein the subset is a Galois Field GF(2P) with p < q.
However, Elia, in an analogous art, teaches wherein each symbol of the plurality of symbols is an element of a Galois Field GF(2q) comprising 2q elements, wherein coefficients of each ELP of the reduced set of ELPs belong to a subset of the Galois Field GF(2q), wherein the subset is a Galois Field GF(2P) with p < q (Elia, para. [0038], lines 1-4, “the coefficients of the polynomial will often be binary numbers, i.e., the coefficients will be elements of GF(2), and the polynomial will be evaluated in an element of an extension field GF(2m) with m>1”).
Brueggen and Elia are both considered to be analogous to the claimed invention because both are in the same field of error correction techniques utilizing polynomials.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Brueggen to incorporate the teachings of Elia by including the functionality of using coefficients derived from a Galois Field subset.
The suggestion/motivation for doing so would be to reduce the computational complexity for finite field polynomial processing.
Claims 12, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Brueggen, in view of Wu (US 7,793,195).
Regarding claim 12, Brueggen teaches the method of claim 1, wherein identifying, using the indicator ELP, the corrupted group of symbols comprises: performing a plurality of iterations, wherein each iteration updates an iterative ELP based on a respective syndrome value of the plurality of syndrome values (Brueggen, para. [0023] through [0024] teaches Berlekamp-Massey iterations, discrepancy calculations, and iteratively updating of polynomial C(x) until the final ELP is produced); and obtaining the original codeword using the codeword and the final iterative ELP (Brueggen, para. [0024], lines 1-6, “The polynomial C(x) resulting from the final iteration of the Berlekamp-Massey algorithm may be an ELP that may be used to find the locations of L errors in the codeword, where the locations correspond to the inverse roots of the ELP. The final ELP C(x) may be used to correct up to quantity T errors”).
Brueggen fails to teach updating the iterative ELP, obtained after the plurality of iterations, using a difference between the iterative ELP and the indicator ELP, to obtain a final iterative ELP.
However, Wu, in an analogous art, teaches updating the iterative ELP, obtained after the plurality of iterations, using a difference between the iterative ELP and the indicator ELP, to obtain a final iterative ELP (Wu, Abstract, lines 1-5, “Generating a polynomial is disclosed. A prior error locator polynomial, associated with locating errors in encoded data, is obtained. A new error locator polynomial, associated with a test error pattern, is incrementally generated based at least in part on the prior error locator polynomial”; col. 5, lines 34-40, “an error locator polynomial is generated for test error pattern 208 based on the error locator polynomial associated with initial dataword 200. The error locator polynomial for test error pattern 209 is based on that for 208 and similarly the error locator polynomial for test error pattern 210 is based on that for 209”).
Brueggen and Wu are both considered to be analogous to the claimed invention because both are in the same field of Reed-Solomon/ECC decoding using error locator polynomials.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Brueggen to incorporate the teachings of Wu by including the functionality of having an incremental error locator polynomial generation techniques.
The suggestion/motivation for doing so would be to reduce decoding complexity, processing latency, and improve decoding efficiency.
Claim 18 is a system with limitations similar to the method of claim 12, and is rejected under the same rationale.
Regarding claim 20, Brueggen teaches a system comprising: a plurality of memory devices; a first set of one or more processing circuits to: receive, from the plurality of memory devices, a codeword comprising a plurality of symbols, wherein each of the plurality of symbols is received from a corresponding memory device of the plurality of memory devices (Brueggen, para. [0014], lines 2-7, “a list decoder circuit may include a Berlekamp-Massey algorithm [BMA] circuit to generate a series of error locator polynomials by processing trial decodes in parallel using syndromes corresponding to symbol group erasure iterations of a codeword provided by a plurality of memory devices”), and wherein the codeword has at least one error relative to an original codeword stored in the plurality of memory devices (Brueggen, para. [0012], lines 7-10, “the disclosed example list decoder circuit implementations are capable of detecting and correcting errors contributed by other memory devices, even in the presence of errors contributed by the failed memory device”); and compute, using the codeword, a plurality of syndrome values characterizing a difference between the codeword and the original codeword (Brueggen, Fig.3, syndrome calculation circuit 302 & erasure syndrome calculation circuit 306); a second set of one or more processing circuits to: identify a reduced set of error locator polynomials (ELPs) for the codeword (Brueggen, para. [0030] teaches generating a series of ELPs using trial decodes and the Berlekamp-Massey algorithm; para. [0045] teaches using device status information to forego certain trial decodes and only process trial decodes corresponding to candidate failed devices, which equates to reducing the set of candidate ELPs), wherein each ELP of the reduced set of ELPs is associated with (i) at least one potential error within a respective group of symbols of a plurality of groups of symbols of the codeword (Brueggen, para. [0031], lines 2-4, “A trial erasure decode may be a trial decode in which a symbol group contributed by a memory device to the codeword is erased”; each trial decode generates a corresponding ELP associated with a memory device symbol group) and (ii) absence of potential errors outside the respective group of symbols (Brueggen, para. [0054] teaches the ELP evaluation circuit evaluating whether a resulting error pattern contains errors in a “soft” failed memory device and no errors anywhere else); and select, in view of the plurality of syndrome values, an indicator ELP from the reduced set of ELPs (Brueggen, para. [0041], lines 18-20, “The ELP resulting from the non-trial erasure decode may be passed to MUX circuit 210, which may provide the ELP to an ELP evaluation circuit”; para. [0062], lines 7-10, “the ELP generated from the trial non-erasure decode may be immediately selected by the MUX circuit and passed to the ELP evaluation circuit”), wherein the indicator ELP is associated with a corrupted group of symbols of the plurality of groups of symbols, the corrupted group of symbols having at least one error (Brueggen, para. [0054], lines 5-10, “The ELP evaluation circuit may evaluate the ELP to determine if the resulting error pattern has errors in the data from the ‘soft’ failed memory device and no errors anywhere else. If so, it is considered very likely to be the actual error pattern and the BMA circuit may terminate the other trial decodes”); and a third set of one or more processing circuits to: perform a plurality of iterations, wherein each iteration updates an iterative ELP based on a respective syndrome value of the plurality of syndrome values (Brueggen, para. [0023] through [0024] teaches Berlekamp-Massey iterations, discrepancy calculations, and iteratively updating of polynomial C(x) until the final ELP is produced); and obtain the original codeword using the codeword and the final iterative ELP (Brueggen, para. [0024], lines 1-6, “The polynomial C(x) resulting from the final iteration of the Berlekamp-Massey algorithm may be an ELP that may be used to find the locations of L errors in the codeword, where the locations correspond to the inverse roots of the ELP. The final ELP C(x) may be used to correct up to quantity T errors”).
Brueggen fails to teach update the iterative ELP, obtained after the plurality of iterations, using a difference between the iterative ELP and the indicator ELP, to obtain a final iterative ELP.
However, Wu, in an analogous art, teaches update the iterative ELP, obtained after the plurality of iterations, using a difference between the iterative ELP and the indicator ELP, to obtain a final iterative ELP (Wu, Abstract, lines 1-5, “Generating a polynomial is disclosed. A prior error locator polynomial, associated with locating errors in encoded data, is obtained. A new error locator polynomial, associated with a test error pattern, is incrementally generated based at least in part on the prior error locator polynomial”; col. 5, lines 34-40, “an error locator polynomial is generated for test error pattern 208 based on the error locator polynomial associated with initial dataword 200. The error locator polynomial for test error pattern 209 is based on that for 208 and similarly the error locator polynomial for test error pattern 210 is based on that for 209”).
Brueggen and Wu are both considered to be analogous to the claimed invention because both are in the same field of Reed-Solomon/ECC decoding using error locator polynomials.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Brueggen to incorporate the teachings of Wu by including the functionality of having an incremental error locator polynomial generation techniques.
The suggestion/motivation for doing so would be to reduce decoding complexity, processing latency, and improve decoding efficiency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US 2011/0055668) teaches determining coefficients of an error locator polynomial.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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