Prosecution Insights
Last updated: October 23, 2026
Application No. 18/875,601

A PATTERNING DEVICE VOLTAGE BIASING SYSTEM FOR USE IN EUV LITHOGRAPHY

Final Rejection §102§103
Filed
Dec 16, 2024
Priority
May 31, 2023 — EU 23176443.2 +2 more
Examiner
RIDDLE, CHRISTINA A
Art Unit
2882
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
ASML Holding N.V.
OA Round
2 (Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
1y 1m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
761 granted / 940 resolved
+13.0% vs TC avg
Moderate +14% lift
Without
With
+14.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
31 currently pending
Career history
995
Total Applications
across all art units

Statute-Specific Performance

§101
2.7%
-37.3% vs TC avg
§103
47.5%
+7.5% vs TC avg
§102
21.1%
-18.9% vs TC avg
§112
18.9%
-21.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 940 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status Acknowledgment is made of the amendment filed on 8/10/2026, which amended claims 69, 73-77, 79, 80, 82, 83, 85, and 88, cancelled claim 84, and added new claims 89-93. Claims 63-83 and 85-93 are currently pending. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a first current-limiting component” in claim 86. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 69, 79, 81 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US PGPub 2018/0164694, Kim hereinafter). Regarding claim 69, Kim discloses a patterning device voltage biasing system for use in a lithographic apparatus (Figs. 1-15, 17, paras. [0032], [0046]-[0047], [0053]-[0054], [0056]-[0065], [0080]-[0091], [0096], [0101]-[0110], a reticle stage power source 300, or voltage sources supplies voltage to the surface of the reticle 210), the patterning device voltage biasing system comprising: a patterning device configured to impart a pattern to a beam of radiation, the patterning device comprising a patterning surface with a pattern thereon (Figs. 1-15, 17, paras. [0008]-[0009], [0030], [0032], [0036], [0039]-[0040], [0135], reticle 210 includes a pattern region 215 formed on the first surface 210a that patterns exposure light projected to a wafer); and a voltage source (Figs. 1-15, 17, paras. [0032], [0046]-[0047], [0053]-[0054], [0056]-[0065], [0080]-[0091], [0096], [0101]-[0110], a reticle stage power source 300 or voltage sources 1-3), wherein the patterning device voltage biasing system is configured such that a voltage is applied to the patterning surface of the patterning device by the voltage source (Figs. 1-15, 17, paras. [0032], [0039]-[0042], [0046]-[0047], [0052]-[0054], [0056]-[0065], [0068]-[0069], [0074], [0080]-[0091], [0096], [0101]-[0110], a reticle stage power source 300 or voltage sources 1-3 applies voltage to the first surface 210a on which the pattern region 215 is formed), and wherein the voltage source is configured to apply the voltage to the patterning surface to reduce positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface (the limitation “wherein the voltage source is configured to apply the voltage to the patterning surface to reduce positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface” is functional language that recites the manner of operating the device and does not differentiate the claimed apparatus from the structure as taught by Kim. See MPEP 2114. Figs. 1-15, 17, paras. [0032], [0039]-[0042], [0046]-[0047], [0052]-[0054], [0056]-[0065], [0068]-[0069], [0074], [0080]-[0091], [0096], [0101]-[0110], a reticle stage power source 300 or voltage sources 1-3 applies voltage to the first surface 210a on which the pattern region 215 is formed). Regarding claim 79, Kim discloses wherein the bias voltage is negative or positive (Figs. 1-15, 17, paras. [0052]-[0058], [0060], [0063]-[0064], [0068]-[0069], [0072]-[0073], [0080]-[0082], [0090]-[0091], the power source 300 or voltage source provides a negative voltage or positive voltage to the first surface 210a with the pattern region 215 of the reticle 210). Regarding claim 81, Kim discloses a lithographic apparatus (Figs. 1-15, 17, paras. [0032], [0111]-[0119], [0132]-[0136], the lithography apparatus) comprising: the patterning device voltage biasing system of claim 69 (see claim 69 rejection above, Figs. 1-15, 17, paras. [0032], [0032], [0039]-[0042], [0046]-[0047], [0052]-[0054], [0056]-[0065], [0068]-[0069], [0074], [0080]-[0091], [0096], [0101]-[0110], 0111]-[0119], [0132]-[0136], the lithography apparatus includes the power source 300 or voltage source and the reticle 210). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 70 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 69 above, and further in view of Yonekawa (US PGPub 2020/0176275). Regarding claim 70, Kim discloses further comprising a conductive member electrically conductive to the voltage source (Figs. 3, 4A, 4B, 4C, 5-8, 10-12, 14, paras. [0055]-[0063], [0078]-[0084], [0100]-[0105], [0132]-[0133], the reticle stage power source 300 is connected to the first surface 210a including pattern region 215 of the reticle 210 through reticle via 213, sidewall conductive film 214, connection pad 216, or the voltage source is connected to one or more conductors 231, 232 protruding from the first surface 210a), but Kim does not appear to explicitly describe wherein the patterning device voltage system is capable of transitioning between a first arrangement and a second arrangement; in the first arrangement, the conductive member is in contact with the patterning surface such that the voltage is applied to the patterning surface; and in the second arrangement, the conductive member is distanced from the patterning surface. Yonekawa discloses a conductive member electrically connected to a voltage source (Figs. 3-5, 7-8, 10, abstract, paras. [0006], [0050]-[0053], [0058], [0063]-[0064], [0067]-[0070], the contactor 63, 73 is connected to a power supply unit 64, 74), wherein: a voltage system is capable of transitioning between a first arrangement and a second arrangement (Figs. 3-5, 7-8, 10, abstract, paras. [0006], [0050]-[0053], [0058], [0063]-[0064], [0067]-[0070], the contactor 63, 73 is arranged in a state in contact with a plate and in a state separated from the plate); in the first arrangement, the conductive member is in contact with the surface such that the voltage is applied to the surface (Figs. 3-5, 7-8, 10, abstract, paras. [0050]-[0053], [0058], [0063]-[0064], [0070], the contactor 63, 73 and plate are in contact such that the contactor of the charging unit applies voltage to the plate via the contactor); and in the second arrangement, the conductive member is distanced from the surface (Figs. 3-5, 7-8, 10, abstract, paras. [0006], [0053], [0058], [0063]-[0064], [0070], the contactor 63, 73 and plate are separated). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included a system capable of transitioning between a first arrangement and a second arrangement; in the first arrangement, the conductive member is in contact with the surface such that the voltage is applied to the surface; and in the second arrangement, the conductive member is distanced from the surface as taught by Yonekawa in the patterning device voltage system as taught by Kim since including patterning device voltage system is capable of transitioning between a first arrangement and a second arrangement; in the first arrangement, the conductive member is in contact with the patterning surface such that the voltage is applied to the patterning surface; and in the second arrangement, the conductive member is distanced from the patterning surface is commonly used to effectively remove particles using a device that applies a reproducible, uniform charge distribution by allowing control of the state of the electric potential of the surface contacted (Yonekawa, paras. [0005]-[0006], [0053]). Claims 71 and 72 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 69 above, and further in view of Hoeks et al. (US PGPub 2004/0114124, Hoeks hereinafter). Regarding claim 71, Kim discloses wherein: the patterning device further comprises a non-patterning surface opposite the patterning surface (Figs. 1-15, 17, paras. [0039], [0041], [0045]-[0047], [0052], [0057], [0065], the reticle 210 includes second surface 210b opposite to first surface 210a with pattern region 215); the patterning device voltage biasing system further comprises a patterning device holder (Figs. 1-15, 17, paras. [0030], [0034], [0037]-[0038], [0132]-[0133], reticle stage 300 chucks the reticle 210); at least a portion of the non-patterning surface is electrically connected to the voltage source (Figs. 1-15, 17, paras. [0039], [0041], [0045]-[0047], [0052], [0055]-[0058], [0061]-[0065], the power source 300 is connected to second surface 210b); and the patterning surface and the non-patterning surface are electrically connected (Figs. 1-5, 15, 17, paras. [0055]-[0064], a reticle via 213, sidewall conductive film 214 electrically connects the films 211 and 212 on surfaces 210a and 210b). Kim does not appear to explicitly describe the patterning device holder comprises a plurality of burls; distal ends of one or more of the plurality of burls are in contact with the non-patterning surface of the patterning device; at least a portion of the non-patterning surface is electrically connected to the voltage source via one or more of the plurality of burls. Hoeks discloses the patterning device holder comprises a plurality of burls (Fig. 3, paras. [0016]-[0018], [0070]-[0072], claim 12, clamping chuck 30 comprises pins 32); distal ends of one or more of the plurality of burls are in contact with the non-patterning surface of the patterning device (Fig. 3, paras. [0016]-[0018], [0064], [0070]-[0072], claim 12, clamping chuck 30 includes conductive pins 32 in contact with the electrode 20 of substrate 18); at least a portion of the non-patterning surface is electrically connected to the voltage source via one or more of the plurality of burls (Fig. 3, paras. [0016]-[0018], [0064], [0070]-[0072], claim 12, clamping chuck 30 includes conductive pins 32 in contact with the electrode 20 of substrate 18 such that the electrode 20 is electrically connected to conductor 36 via pins 32). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included the patterning device holder comprises a plurality of burls; distal ends of one or more of the plurality of burls are in contact with the non-patterning surface of the patterning device; at least a portion of the non-patterning surface is electrically connected to the voltage source via one or more of the plurality of burls as taught by Hoeks in the patterning device voltage biasing system with the voltage source, the non-patterning surface, and the patterning device holder as taught by Kim since including the patterning device holder comprises a plurality of burls; distal ends of one or more of the plurality of burls are in contact with the non-patterning surface of the patterning device; at least a portion of the non-patterning surface is electrically connected to the voltage source via one or more of the plurality of burls is commonly used to effectively clamp the patterning device while allowing quick release to improve throughput (Hoeks, abstract, paras. [0013]-[0019]). Regarding claim 72, Kim discloses wherein: the patterning device further comprises a non-patterning surface on an opposite side of the patterning device to the patterning surface (Figs. 1-15, 17, paras. [0039], [0041], [0045]-[0047], [0052], [0057], [0065], the reticle 210 includes second surface 210b opposite to first surface 210a with pattern region 215); the patterning surface and non-patterning surface are substantially electrically isolated from one another (Fig. 4C, paras. [0059]-[0061], [0065], the first reticle conductive film 211 is not electrically connected to the second reticle conductive film 212); the patterning device voltage biasing system further comprising a patterning device holder (Figs. 1-15, 17, paras. [0030], [0034], [0037]-[0038], [0132]-[0133], reticle stage 300 chucks the reticle 210); and electrically connecting the non-patterning surface to the voltage source (Figs. 1-15, 17, paras. [0039], [0041], [0045]-[0047], [0052], [0055]-[0058], [0061]-[0065], the power source 300 is connected to second surface 210b having second reticle conductive film 212). Kim does not appear to explicitly describe the patterning device holder comprises a plurality of burls; distal ends of one or more of the plurality of burls are arranged to contact with the non-patterning surface of the patterning device; and one or more of the plurality of burls are configured to electrically connect the non-patterning surface. Hoeks discloses the patterning device holder comprises a plurality of burls (Fig. 3, paras. [0016]-[0018], [0070]-[0072], claim 12, clamping chuck 30 comprises pins 32); distal ends of one or more of the plurality of burls are arranged to contact with the non-patterning surface of the patterning device (Fig. 3, paras. [0016]-[0018], [0064], [0070]-[0072], claim 12, clamping chuck 30 includes conductive pins 32 in contact with the electrode 20 of substrate 18); one or more of the plurality of burls are configured to electrically connect the non-patterning surface to the voltage source (Fig. 3, paras. [0016]-[0018], [0064], [0070]-[0072], claim 12, clamping chuck 30 includes conductive pins 32 in contact with the electrode 20 of substrate 18 such that the electrode 20 is electrically connected to conductor 36 via pins 32). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included the patterning device holder comprises a plurality of burls; distal ends of one or more of the plurality of burls are arranged to contact with the non-patterning surface of the patterning device; and one or more of the plurality of burls are configured to electrically connect the non-patterning surface as taught by Hoeks in the patterning device voltage biasing system with the voltage source, the non-patterning surface, and the patterning device holder as taught by Kim since including the patterning device holder comprises a plurality of burls; distal ends of one or more of the plurality of burls are arranged to contact with the non-patterning surface of the patterning device; and one or more of the plurality of burls are configured to electrically connect the non-patterning surface is commonly used to effectively clamp the patterning device while allowing quick release to improve throughput (Hoeks, abstract, paras. [0013]-[0019]). Claim 73 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as modified by Hoeks as applied to claim 71 and above, and further in view of Amamiya (JP2011-040464) Regarding claim 73, Kim as modified by Hoeks discloses the patterning surface and the voltage source (Figs. 1-15, 17, paras. [0032], [0039]-[0042], [0046]-[0047], [0052]-[0054], [0056]-[0065], [0068]-[0069], [0074], [0080]-[0091], [0096], [0101]-[0110], a reticle stage power source 300 or voltage sources 1-3 applies voltage to the first surface 210a on which the pattern region 215 is formed), but Kim as modified by Hoeks does not appear to explicitly describe wherein the patterning surface and the voltage source are connected by a first current-limiting component, wherein the first current-limiting component comprises at least one of a resistor, and inductor, a diode or a switch. Amamiya discloses wherein the patterning surface and the voltage source are connected by a first current-limiting component, wherein the first current-limiting component comprises at least one of a resistor, an inductor, a diode, or a switch (Figs. 7, 9, abstract, pages 3-4 and 9-10 of the attached English translation, a switch (see Figs. 7a-b and 9a-c) is arranged between the voltage source and the patterning surface of the mask 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included wherein the patterning surface and the voltage source are connected by a first current-limiting component, wherein the first current-limiting component comprises at least one of a resistor, an inductor, a diode, or a switch as taught by Amamiya in the patterning device voltage biasing system as taught by Kim as modified by Hoeks since including wherein the patterning surface and the voltage source are connected by a first current-limiting component, wherein the first current-limiting component comprises at least one of a resistor, an inductor, a diode, or a switch is commonly used to quickly control the polarity of voltage on the surface of the mask to facilitate removal of neutral particles from the surface of the mask (Amamiya, page 3, last paragraph, pages 9-10). Claim 74 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as modified by Hoeks in view of Amamiya as applied to claim 73 above, and further in view of Van der Wilk et al. (US PGPub 2015/0103325, Van Der Wilk hereinafter). Regarding claim 74, Kim as modified by Hoeks in view of Amamiya discloses the plurality of burls and the voltage source (Kim, Figs. 1-15, 17, paras. [0032], [0039]-[0042], [0046]-[0047], [0052]-[0054], [0056]-[0065], [0068]-[0069], [0074], [0080]-[0091], [0096], [0101]-[0110], a reticle stage power source 300 or voltage sources 1-3 applies voltage to the first surface 210a on which the pattern region 215 is formed, and as modified by Hoeks, Fig. 3, paras. [0016]-[0018], [0064], [0070]-[0072], claim 12, clamping chuck 30 includes conductive pins 32 in contact with the electrode 20 of substrate 18 such that the electrode 20 is electrically connected to conductor 36 via pins 32), Kim as modified by Hoeks in view of Amamiya does not appear to explicitly describe wherein the first current-limiting component is disposed between the plurality of burls and the voltage source. Van der Wilk discloses wherein the first current-limiting component is disposed between the plurality of burls and the voltage source (Figs. 6-8, paras. [0083], [0085], [0089], [0093], [0095]-[0111], the electrostatic clamp 21 includes resistive portion 23 between burls 25 and voltage supply 28). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included wherein the first current-limiting component is disposed between the plurality of burls and the voltage source as taught by Van Der Wilk in the patterning device voltage biasing system as taught by Kim as modified by Hoeks in view of Amamiya since including wherein the first current-limiting component is disposed between the plurality of burls and the voltage source is commonly used to structurally support the surface on which burls of the holder are formed while minimizing the effect of defects on the clamping pressure (Van Der Wilk, paras. [0088], [0102]-[0103]). Claim 76 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as modified by Hoeks as applied to claim 71 above, and further in view of Van der Wilk. Regarding claim 76, Kim as modified by Hoeks discloses wherein the non-patterning surface is electrically connected to one or more of the plurality of burls (Kim, Figs. 1-15, 17, paras. [0039], [0041], [0045]-[0047], [0052], [0055]-[0058], [0061]-[0065], the power source 300 is connected to second surface 210b having second reticle conductive film 212, and as modified by Hoeks, Fig. 3, paras. [0016]-[0018], [0064], [0070]-[0072], claim 12, clamping chuck 30 includes conductive pins 32 in contact with the electrode 20 of substrate 18), but Kim as modified by Hoeks does not appear to explicitly describe wherein the non-patterning surface is electrically connected to a ground via the one or more of the plurality of burls. Van Der Wilk discloses wherein the non-patterning surface is electrically connected to a ground via the one or more of the plurality of burls (Figs. 6-8, paras. [0079], [0083]-[0084], [0093]-[0097], [0115], burls 25 are connected to ground 29, and burls 25 connect to the non-patterning surface of the mask held in plane 26). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included the non-patterning surface is electrically connected to the ground via the one or more of the plurality of burls as taught by Van Der Wilk in the patterning device voltage biasing system as taught by Kim as modified by Hoeks since including wherein the non-patterning surface is electrically connected to the ground via the one or more of the plurality of burls is commonly used to control the clamping force and avoid undesired accumulation of charges (Van Der Wilk, paras. [0082], [0084], [0093]-[0094], [0115]). Claim 77 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as modified by Hoeks as applied to claim 71 above, and further in view of Burkhart (US Patent No. 5,764,471). Regarding claim 77, Kim as modified by Hoeks does not appear to explicitly describe wherein the patterning device voltage biasing system further comprises a mode-changing switch configured such that the non-patterning surface is either connected to (i) the power supply via the one or more of the plurality of burls or (ii) a ground via the one or more of the plurality of burls. Burkhart discloses wherein the patterning device voltage biasing system further comprises a mode-changing switch (Figs. 1-2, col. 3, lines 27-38, col. 4, lines 49-67, col. 5, lines 1-61, the high voltage power supply 126 is either activated or deactivated, and switches 136, 138, 140 are used during dechuck) configured such that the non-patterning surface is either connected to (i) the power supply via the one or more of the plurality of burls (Figs. 1-2, col. 3, lines 27-38, col. 4, lines 49-67, col. 5, lines 1-61, the power supply 126 is connected to support members 120 and the wafer 108 in a first mode when the power supply is active) or (ii) a ground via the one or more of the plurality of burls (Figs. 1-2, col. 3, lines 27-38, col. 4, lines 49-67, col. 5, lines 1-61, a switch 136 connects the biased support elements 120 and wafer 108 to earth ground when closed). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included wherein the patterning device voltage biasing system further comprises a mode-changing switch configured such that the non-patterning surface is either connected to (i) the power supply via the one or more of the plurality of burls or (ii) a ground via the one or more of the plurality of burls as taught by Burkhart with the non-patterning surface in the patterning device voltage biasing system as taught by Kim as modified by Hoeks since including wherein the patterning device voltage biasing system further comprises a mode-changing switch configured such that the non-patterning surface is either connected to (i) the power supply via the one or more of the plurality of burls or (ii) a ground via the one or more of the plurality of burls is commonly used to remove residual charge from an object held by an electrostatic support to quickly remove the object from the support (Burkhart, col. 2, lines 24-28, col. 5, lines 49-55). Claim 78 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as modified by Hoeks in view of Van Der Wilk as applied to claim 76 above, and further in view of Burkhart (US Patent No. 5,764,471). Regarding claim 78, although Kim as modified by Hoeks in view of Van Der Wilk discloses wherein the patterning device is loaded onto the patterning device holder and/or unloaded from the patterning device holder (Kim, Figs. 1-15, 17, paras. [0030], [0034], [0037]-[0038], [0132]-[0133], reticle stage 300 chucks the reticle 210), Kim as modified by Hoeks in view of Van Der Wilk does not appear to explicitly describe wherein the patterning device voltage biasing system is configured such that the non-patterning surface is connected to the ground via the one or more of the plurality of burls while the patterning device is loaded onto the patterning device holder and/or unloaded from the patterning device holder. Burkhart discloses the non-patterning surface is connected to the ground via the one or more of the plurality of burls while the workpiece is loaded onto the holder and/or unloaded from the holder (Figs. 1-2, col. 3, lines 27-38, col. 4, lines 49-67, col. 5, lines 1-61, a switch 136 connects the biased support elements 120 and wafer 108 to earth ground when closed when the wafer is to be removed from the chuck). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included the non-patterning surface is connected to the ground via the one or more of the plurality of burls while the workpiece is loaded onto the holder and/or unloaded from the holder as taught by Burkhart with the patterning device and the patterning device holder in the patterning device voltage biasing system as taught by Kim as modified by Hoeks in view of Van Der Wilk since including wherein the patterning device voltage biasing system is configured such that the non-patterning surface is connected to the ground via the one or more of the plurality of burls while the patterning device is loaded onto the patterning device holder and/or unloaded from the patterning device holder is commonly used to remove residual charge from an object held by an electrostatic support to quickly remove the object from the support (Burkhart, col. 2, lines 24-28, col. 5, lines 49-55). Claims 80, 90, and 91 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 79 above, and further in view of Wu et al. (US PGPub 2014/0253887, Wu hereinafter). Regarding claim 80, Kim discloses wherein the voltage source is configured to supply the negative bias voltage to the patterning surface with a magnitude (Figs. 1, 3, 4A, 4B, 4C, 5-8, 10-12, 14, 15, 17, paras. [0052]-[0058], [0060], [0063]-[0064], [0068]-[0069], [0072]-[0073], [0080]-[0082], [0090]-[0091], the power source 300 or voltage source provides a negative voltage to the first surface 210a with the pattern region 215 of the reticle 210), and/or the voltage source is configured to supply the positive bias voltage to the patterning surface with a magnitude (Figs. 1, 3, 4A, 4B, 4C, 5-8, 10-12, 14, 15, 17, paras. [0046], [0063], [0084], [0136], the power source 300 supplies a positive voltage to first surface 210a with the pattern region 215 of the reticle 210), but Kim does not appear to explicitly describe wherein: the voltage source is configured to supply the negative bias voltage to the patterning surface with a magnitude that is greater than 0.5V and less than 10 V, and/or the voltage source is configured to supply the positive bias voltage to the patterning surface with a magnitude that is greater than 1 V and less than 100 V. Wu discloses wherein: the voltage source is configured to supply the negative bias voltage with a magnitude that is greater than 0.5V and less than 10 V, and/or the voltage source is configured to supply the positive bias voltage with a magnitude that is greater than 1 V and less than 100 V (paras. [0025], [0035], the voltage applied to the conductive plate is between 50 Volts and 500 Volts). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included the voltage source is configured to supply the negative bias voltage with a magnitude that is greater than 0.5V and less than 10 V, and/or the voltage source is configured to supply the positive bias voltage with a magnitude that is greater than 1 V and less than 100 V as taught by Wu as the bias voltage supplied by the voltage source to the patterning surface in the patterning device voltage biasing system as taught by Kim since including the voltage source is configured to supply the negative bias voltage with a magnitude that is greater than 0.5V and less than 10 V, and/or the voltage source is configured to supply the positive bias voltage with a magnitude that is greater than 1 V and less than 100 V is commonly used to establish the required electric potential to effectively influence particles from the surface of the photomask (Wu, para. [0035]) and since, absent evidence of criticality, it would have only required routine experimentation to have optimized the magnitude of the negative bias voltage or positive bias voltage in the patterning device voltage biasing system as taught by Kim to the negative bias voltage with a magnitude that is greater than 0.5V and less than 10 V, and/or the positive bias voltage with a magnitude that is greater than 1 V and less than 100 V as suggested by Wu to have determined the voltage necessary to protect a mask from contamination in an EUV system (Wu, paras. [0008]-[0009]). "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP 2144.05, subsection II. Regarding claim 90, Kim as modified by Wu discloses wherein the voltage source is configured to supply the negative bias voltage to the patterning surface with a magnitude that is greater than 50 Volts and less than 500 Volts (Kim, Figs. 1, 3, 4A, 4B, 4C, 5-8, 10-12, 14, 15, 17, paras. [0052]-[0058], [0060], [0063]-[0064], [0068]-[0069], [0072]-[0073], [0080]-[0082], [0090]-[0091], the power source 300 or voltage source provides a negative voltage to the first surface 210a with the pattern region 215 of the reticle 210, and as modified by Wu, paras. [0025], [0035], the voltage applied to the conductive plate is between 50 Volts and 500 Volts), and/or the voltage source is configured to supply the positive bias voltage to the patterning surface with a magnitude that is greater than 50 Volts and less than 500 Volts (Kim, Figs. 1, 3, 4A, 4B, 4C, 5-8, 10-12, 14, 15, 17, paras. [0046], [0063], [0084], [0136], the power source 300 supplies a positive voltage to first surface 210a with the pattern region 215 of the reticle 210, and as modified by Wu, paras. [0025], [0035], the voltage applied to the conductive plate is between 50 Volts and 500 Volts), but Kim as modified by Wu does not appear to explicitly describe wherein: the voltage source is configured to supply the negative bias voltage to the patterning surface with a magnitude that is greater than 1V and less than 5 V, and/or the voltage source is configured to supply the positive bias voltage to the patterning surface with a magnitude that is greater than 5 V and less than 50 V. However, since Kim as modified by Wu discloses the general conditions of the magnitude of the bias voltage and absent evidence of criticality, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included optimizing the magnitude of the bias voltage supplied to the patterning surface in the patterning device voltage biasing system as taught by Kim as modified by Wu to obtain the negative bias voltage supplied to the patterning surface with a magnitude that is greater than 1 V and less than 5 V, and/or the positive bias voltage to the patterning surface is supplied with a magnitude that is greater than 5 V and less than 50 V since it would have only required routine skill to have determined the voltage necessary to protect a mask from contamination in an EUV system (Wu, paras. [0008]-[0009]). "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP 2144.05, subsection II. Regarding claim 91, Kim as modified by Wu discloses the general conditions of wherein the voltage source is configured to supply the negative bias voltage to the patterning surface with a magnitude that is greater than 50 V and less than 500 V (Kim, Figs. 1, 3, 4A, 4B, 4C, 5-8, 10-12, 14, 15, 17, paras. [0052]-[0058], [0060], [0063]-[0064], [0068]-[0069], [0072]-[0073], [0080]-[0082], [0090]-[0091], the power source 300 or voltage source provides a negative voltage to the first surface 210a with the pattern region 215 of the reticle 210, and as modified by Wu, paras. [0025], [0035], the voltage applied to the conductive plate is between 50 Volts and 500 Volts), Kim as modified by Wu does not appear to explicitly describe greater than 1 V and less than 3 V. However, since Kim as modified by Wu discloses the general conditions of the magnitude of the bias voltage and absent evidence of criticality, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included optimizing the magnitude of the bias voltage supplied to the patterning surface in the patterning device voltage biasing system as taught by Kim as modified by Wu to obtain the negative bias voltage supplied to the patterning surface with a magnitude that is greater than 1 V and less than 3 V since it would have only required routine skill to have determined the voltage necessary to protect a mask from contamination in an EUV system (Wu, paras. [0008]-[0009]). "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP 2144.05, subsection II. Claims 82, 86, and 87 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Levinson et al. (US Patent No. 6,984,475, Levinson hereinafter). Regarding claim 82, Kim discloses a method of reducing contamination on a patterning surface of a patterning device in a lithographic apparatus (Figs. 1-15, 17, paras. [0006], [0032], [0046]-[0047], [0053]-[0054], [0056]-[0065], [0080]-[0091], [0096], [0101]-[0110], a reticle stage power source 300, or voltage sources supplies voltage to the surface of the reticle 210 to prevent adsorption of particles onto the reticle), the method comprising: contacting such that a conductive member is brought into contact with the patterning surface (Figs. 3, 4A, 4B, 4C, 5-8, 10-12, 14, paras. [0055]-[0063], [0078]-[0084], [0100]-[0105], [0132]-[0133], the reticle stage power source 300 is connected to the first surface 210a including pattern region 215 of the reticle 210 through reticle via 213, sidewall conductive film 214, connection pad 216, or the voltage source is connected to one or more conductors 231, 232 protruding from the first surface 210a); a voltage biasing in which a voltage is provided to the patterning surface from a voltage source, via the conductive member (Figs. 1, 3, 4A, 4B, 4C, 5-8, 10-12, 14, 15, 17, paras. [0032], [0039]-[0042], [0046]-[0047], [0052]-[0054], [0056]-[0065], [0068]-[0069], [0074], [0080]-[0091], [0096], [0101]-[0110], [0132]-[0133], a reticle stage power source 300 or voltage sources 1-3 applies voltage to the first surface 210a on which the pattern region 215 is formed). Although Kim discloses wherein the providing the voltage reduces positive charging of the patterning surface (Figs. 1, 3, 4A, 4B, 4C, 5-8, 10-12, 14, 15, 17, paras. [0005]-[0006], [0046]-[0047], [0052]-[0054], [0056]-[0065], [0068]-[0069], [0074], [0080]-[0091], [0096], [0101]-[0110], [0132]-[0133], negative voltage and positive voltage is supplied to the first surface of the reticle having the pattern and particles are prevented from adsorption), Kim does not appear to explicitly describe wherein providing the voltage reduces positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface. Levinson discloses a voltage biasing in which a voltage is provided to the patterning surface from a voltage source, via the conductive member (Figs. 4-10, col. 4, line 50-col. 5, line 5, col. 5, lines 27-63, col. 7, lines 40-67, col. 8, lines 1-2, lines 51-67, col. 9, lines 55-65, col. 10, lines 55-67, the region 50, 70, 102, 120, 136 is connected to a ground potential 52, 72, 104, 122, 142 or other desired voltage potential); wherein providing the voltage reduces positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface (Figs. 3-10, col. 2, lines 8-19, col. 4, lines 50-67, col. 5, lines 1-4, col. 5, lines 27-63, col. 6, lines 57-67, col. 7, lines 40-67, col. 8, lines 1-2, lines 51-67, col. 9, lines 55-65, col. 10, lines 55-67, connection to the ground potential or other desired voltage potential reduces charging owing to photoelectrons generated by EUV energy). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included wherein providing the voltage reduces positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface as taught by Levinson in the method as taught by Kim since including wherein providing the voltage reduces positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface is commonly used to implement EUV lithography using an EUV mask to improve resolution for increased fabricated pattern density while improving the protection of the mask from damage, thereby reducing imaging defects (Levinson, col. 1, lines 35-46, col. 2, lines 8-40). Regarding claim 86, Kim as modified by Levinson discloses further comprising restricting the current in the patterning surface using a first current-limiting component disposed between the voltage source and the patterning surface (Levinson, Figs. 8-10, col. 4, lines 3-19, col. 8, lines 1-2, lines 30-67, col. 9, lines 5-15, lines 15-65, col. 10, lines 3-12, lines 13-67, col. 11, lines 4-11, the mask includes a substrate 92, 112, 132 made from glass that limits current from the ground potential or other desired potential and the surface of the mask with reflector film). Regarding claim 87, Kim as modified by Levinson discloses wherein the bias voltage is negative (Kim, Figs. 1, 3, 4A, 4B, 4C, 5-8, 10-12, 14, 15, 17, paras. [0052]-[0058], [0060], [0063]-[0064], [0068]-[0069], [0072]-[0073], [0080]-[0082], [0090]-[0091], the power source 300 or voltage source provides a negative voltage to the first surface 210a with the pattern region 215 of the reticle 210). Claim 83 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Levinson and in view of Hoeks. Regarding claim 83, Kim discloses a method of reducing contamination on a patterning surface of a patterning device in a lithographic apparatus (Figs. 1-15, 17, paras. [0006], [0032], [0046]-[0047], [0053]-[0054], [0056]-[0065], [0080]-[0091], [0096], [0101]-[0110], a reticle stage power source 300, or voltage sources supplies voltage to the surface of the reticle 210 to prevent adsorption of particles onto the reticle), the method comprising: clamping the patterning device with a patterning device support (Figs. 1-15, 17, paras. [0030], [0034], [0037]-[0038], [0132]-[0133], reticle stage 300 chucks the reticle 210), wherein a non-patterning surface of the patterning device disposed on a surface of the patterning device support (Figs. 1-15, 17, paras.[0030], [0034], [0037]-[0041], [0045]-[0047], [0052], [0057], [0061]-[0062], [0065], [0111], [0132]-[0133], the second surface 210b includes reticle conductive film 212 in contact with the reticle stage 300), and the non-patterning surface is opposite the patterning surface (Figs. 1-15, 17, paras. [0039], [0041], [0045]-[0047], [0052], [0057], [0065], the reticle 210 includes second surface 210b opposite to first surface 210a with pattern region 215); and providing a voltage to the patterning surface of the patterning device from a voltage source via the non-patterning surface (Figs. 1, 3, 4A, 4B, 4C, 5-8, 10-12, 14, 15, 17, paras. [0032], [0039]-[0042], [0046]-[0047], [0052]-[0065], [0068]-[0069], [0074], [0080]-[0091], [0096], [0101]-[0110], [0132]-[0133], a reticle stage power source 300 or voltage sources 1-3 applies voltage to the first surface 210a on which the pattern region 215 is formed, and a reticle via 213 or sidewall conductive film 214 electrically connects the films 211 and 212 on surfaces 210a and 210b). Although Kim discloses wherein the providing the voltage reduces positive charging of the patterning surface (Figs. 1, 3, 4A, 4B, 4C, 5-8, 10-12, 14, 15, 17, paras. [0005]-[0006], [0046]-[0047], [0052]-[0054], [0056]-[0065], [0068]-[0069], [0074], [0080]-[0091], [0096], [0101]-[0110], [0132]-[0133], negative voltage and positive voltage is supplied to the first surface of the reticle having the pattern and particles are prevented from adsorption), Kim does not appear to explicitly describe wherein providing the voltage reduces positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface. Kim does not appear to explicitly describe the non-patterning surface is in contact with one or more of a plurality of burls disposed on the patterning device support and providing the voltage to the patterning surface via the one or more of the plurality of burls. Levinson discloses providing a voltage to the patterning surface of the patterning device from a voltage source via the non-patterning surface (Figs. 4-10, col. 4, line 50-col. 5, line 5, col. 5, lines 27-63, col. 7, lines 40-67, col. 8, lines 1-2, lines 51-67, col. 9, lines 55-65, col. 10, lines 55-67, the region 50, 70, 102, 120, 136 is connected to a ground potential 52, 72, 104, 122, 142 or other desired voltage potential), wherein providing the voltage reduces positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface (Figs. 3-10, col. 2, lines 8-19, col. 4, lines 50-67, col. 5, lines 1-4, col. 5, lines 27-63, col. 6, lines 57-67, col. 7, lines 40-67, col. 8, lines 1-2, lines 51-67, col. 9, lines 55-65, col. 10, lines 55-67, connection to the ground potential or other desired voltage potential reduces charging owing to photoelectrons generated by EUV energy). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included wherein providing the voltage reduces positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface as taught by Levinson in the method as taught by Kim since including wherein providing the voltage reduces positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface is commonly used to implement EUV lithography using an EUV mask to improve resolution for increased fabricated pattern density while improving the protection of the mask from damage, thereby reducing imaging defects (Levinson, col. 1, lines 35-46, col. 2, lines 8-40). Kim as modified by Levinson does not appear to explicitly describe the non-patterning surface is in contact with one or more of a plurality of burls disposed on the patterning device support and providing the voltage to the patterning surface via the one or more of the plurality of burls. Hoeks discloses clamping the patterning device with a patterning device support burls (Fig. 3, paras. [0016]-[0018], [0070]-[0072], claim 12, clamping chuck 30 clamps a mask), wherein a non-patterning surface of the patterning device is in contact with one or more of a plurality of burls disposed on a surface of the patterning device support ((Fig. 3, paras. [0016]-[0018], [0064], [0070]-[0072], claim 12, clamping chuck 30 includes conductive pins 32 in contact with the electrode 20 of substrate 18); and providing a voltage to the patterning device from a voltage source via the one or more of the plurality of burls (Fig. 3, paras. [0016]-[0018], [0064], [0070]-[0072], claim 12, clamping chuck 30 includes conductive pins 32 in contact with the electrode 20 of substrate 18 such that the electrode 20 is electrically connected to conductor 36 via pins 32). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included the non-patterning surface is in contact with one or more of a plurality of burls and providing the voltage to the patterning surface via the one or more of the plurality of burls as taught by Hoeks in the patterning device support in the method as taught by Kim as modified by Levinson since including the non-patterning surface is in contact with one or more of a plurality of burls and providing the voltage to the patterning surface of the patterning device via the one or more of the plurality of burls and the non-patterning surface is commonly used to effectively clamp the patterning device while allowing quick release to improve throughput (Hoeks, abstract, paras. [0013]-[0019]). Claim 85 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as modified by Levinson in view of Hoeks as applied to claim 83 and above, and further in view of Burkhart. Regarding claim 85, Kim as modified by Levinson in view of Hoeks discloses the patterning device being loaded onto the patterning device holder and/or the patterning device being unloaded from the patterning device holder (Kim, Figs. 1-15, 17, paras. [0030], [0034], [0037]-[0038], [0132]-[0133], reticle stage 300 chucks the reticle 210f), Kim as modified by Levinson in view of Hoeks does not appear to explicitly describe further comprising, in response to the patterning device being loaded onto the patterning device holder and/or in response to the patterning device being unloaded from the patterning device holder, discharging the patterning device by connecting the patterning device to a ground via the one or more of the plurality of burls. Burkhart discloses in response to the substrate being loaded onto the holder and/or in response to the substrate being unloaded from the holder, discharging the substrate by connecting the substrate to a ground via the one or more of the plurality of burls (Figs. 1-2, col. 3, lines 27-38, col. 4, lines 49-67, col. 5, lines 1-61, a switch 136 connects the biased support elements 120 and wafer 108 to earth ground when closed when the wafer is to be removed from the chuck). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included in response to the substrate being loaded onto the holder and/or in response to the substrate being unloaded from the holder, discharging the substrate by connecting the substrate to a ground via the one or more of the plurality of burls as taught by Burkhart with the patterning device and the patterning device holder in the method as taught by Kim as modified by Levinson in view of Hoeks since including further comprising, in response to the patterning device being loaded onto the patterning device holder and/or in response to the patterning device being unloaded from the patterning device holder, discharging the patterning device by connecting the patterning device to a ground via the one or more of the plurality of burls is commonly used to remove residual charge from an object held by an electrostatic support to quickly remove the object from the support (Burkhart, col. 2, lines 24-28, col. 5, lines 49-55). Claims 88, 92, 93 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as modified by Levinson as applied to claim 82 above, and further in view of Wu et al. (US PGPub 2014/0253887, Wu hereinafter). Regarding claim 88, Kim as modified by Levinson discloses wherein the voltage is provided to the patterning surface with a magnitude (Kim, Figs. 1, 3, 4A, 4B, 4C, 5-8, 10-12, 14, 15, 17, paras. [0052]-[0058], [0060], [0063]-[0064], [0068]-[0069], [0072]-[0073], [0080]-[0082], [0090]-[0091], the power source 300 or voltage source provides a negative voltage to the first surface 210a with the pattern region 215 of the reticle 210, and as modified by Levinson, Figs. 4-10, col. 4, line 50-col. 5, line 5, col. 5, lines 27-63, col. 7, lines 40-67, col. 8, lines 1-2, lines 51-67, col. 9, lines 55-65, col. 10, lines 55-67, the region 50, 70, 102, 120, 136 is connected to a ground potential 52, 72, 104, 122, 142 or other desired voltage potential), but Kim as modified by Levinson does not appear to explicitly describe wherein a magnitude of the voltage provided to the patterning surface is greater than 0.5V and less than 10 V. Wu discloses wherein a magnitude of the voltage provided is greater than 5 V and less than 500 V (paras. [0025], [0035], the voltage applied to the conductive plate is between 50 Volts and 500 Volts). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included wherein a magnitude of the voltage provided is greater than 5 V and less than 500 V as taught by Wu as the voltage supplied by the voltage source to the patterning surface in the method as taught by Kim as modified by Levinson since including wherein a magnitude of the voltage provided is greater than 5 V and less than 500 V is commonly used to establish the required electric potential to effectively influence particles from the surface of the photomask (Wu, para. [0035]). Kim as modified by Levinson in view of Wu does not appear to explicitly describe the voltage is greater than 0.5 V and less than 10 V. Absent evidence of criticality and since Kim as modified by Levinson in view of Wu discloses the general conditions, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included optimized the magnitude of the voltage provided to the patterning surface in the method as taught by Kim as modified by Levinson in view of Wu to obtain the voltage is greater than 0.5 V and less than 10 V since it would have only required routine skill to have determined the voltage necessary to protect a mask from contamination in an EUV system (Wu, paras. [0008]-[0009]). "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP 2144.05, subsection II. Regarding claim 92, Kim as modified by Levinson in view of Wu discloses the general conditions of wherein the magnitude of the voltage provided to the patterning surface is greater than 50 V and less than 500 V (Kim, Figs. 1, 3, 4A, 4B, 4C, 5-8, 10-12, 14, 15, 17, paras. [0052]-[0058], [0060], [0063]-[0064], [0068]-[0069], [0072]-[0073], [0080]-[0082], [0090]-[0091], the power source 300 or voltage source provides a negative voltage to the first surface 210a with the pattern region 215 of the reticle 210, and as modified by Wu, paras. [0025], [0035], the voltage applied to the conductive plate is between 50 Volts and 500 Volts), but Kim as modified by Levinson in view of Wu does not appear to explicitly describe greater than 1 V and less than 5 V. However, since Kim as modified by Levinson in view of Wu discloses the general conditions of the magnitude of the voltage and absent evidence of criticality, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included optimizing the magnitude of the voltage provided to the patterning surface in the method as taught by Kim as modified by Levinson in view of Wu to obtain the voltage provided to the patterning surface with a magnitude that is greater than 1 V and less than 5 V since it would have only required routine skill to have determined the voltage necessary to protect a mask from contamination in an EUV system (Wu, paras. [0008]-[0009]). "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP 2144.05, subsection II. Regarding claim 93, Kim as modified by Levinson in view of Wu discloses the general conditions of wherein the magnitude of the voltage provided to the patterning surface is greater than 50 V and less than 500 V (Kim, Figs. 1, 3, 4A, 4B, 4C, 5-8, 10-12, 14, 15, 17, paras. [0052]-[0058], [0060], [0063]-[0064], [0068]-[0069], [0072]-[0073], [0080]-[0082], [0090]-[0091], the power source 300 or voltage source provides a negative voltage to the first surface 210a with the pattern region 215 of the reticle 210, and as modified by Wu, paras. [0025], [0035], the voltage applied to the conductive plate is between 50 Volts and 500 Volts), but Kim as modified by Levinson in view of Wu does not appear to explicitly describe greater than 1 V and less than 3 V. However, since Kim as modified by Levinson in view of Wu discloses the general conditions of the magnitude of the voltage and absent evidence of criticality, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included optimizing the magnitude of the voltage provided to the patterning surface in the method as taught by Kim as modified by Levinson in view of Wu to obtain the voltage provided to the patterning surface with a magnitude that is greater than 1 V and less than 3 V since it would have only required routine skill to have determined the voltage necessary to protect a mask from contamination in an EUV system (Wu, paras. [0008]-[0009]). "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP 2144.05, subsection II. Claim 89 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as modified by Hoeks in view of Amamiya as applied to claim 73 above, and further in view of Perez-Falcon et al. (US PGPub 2020/0348606, Perez-Falcon hereinafter). Regarding claim 89, Kim as modified by Hoeks in view of Amamiya does not appear to explicitly describe wherein the first current-limiting component comprises the switch and the switch is a timing switch that is configured to electrically disconnect the patterning surface from the voltage source during generation of a pulse of radiation by the lithographic apparatus and electrically connect the patterning surface to the voltage source between pulses of radiation from the lithographic apparatus. Perez-Falcon discloses the first current-limiting component comprises the switch and the switch is a timing switch that is configured to electrically disconnect the surface from the voltage source during generation of a pulse of radiation by the lithographic apparatus and electrically connect the patterning surface to the voltage source between pulses of radiation from the lithographic apparatus (the limitation “is configured to electrically disconnect the patterning surface from the voltage source during generation of a pulse of radiation by the lithographic apparatus and electrically connect the patterning surface to the voltage source between pulses of radiation from the lithographic apparatus” is functional language that recites the manner of operating the claimed patterning device voltage biasing system as drafted and does not differentiate the claimed apparatus from the structure as taught by Perez-Falcon. See MPEP 2114. paras. [0012], [0014], [0067], a switching device is an electronic or optoelectronic switch that provides a signal to selectively connect and disconnect the electrode from a voltage source at preselected intervals). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included the first current-limiting component comprises the switch and the switch is a timing switch that is configured to electrically disconnect the surface from the voltage source during generation of a pulse of radiation by the lithographic apparatus and electrically connect the patterning surface to the voltage source between pulses of radiation from the lithographic apparatus as taught by Perez-Falcon as the switch in the first current-limiting component in the patterning device voltage biasing system as taught by Kim as modified by Hoeks in view of Amamiya since including wherein the first current-limiting component comprises the switch and the switch is a timing switch that is configured to electrically disconnect the patterning surface from the voltage source during generation of a pulse of radiation by the lithographic apparatus and electrically connect the patterning surface to the voltage source between pulses of radiation from the lithographic apparatus is commonly used to improve control over the cleaning operation as desired by the operator. Allowable Subject Matter Claim 75 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter. Regarding claim 75, the prior art of record, either alone or in combination, fails to teach or render obvious wherein the first current-limiting component is formed in the non-patterning surface of the patterning device outside a patterning area. This limitation in combination with all of the other limitations of the parent claims would render the claim non-obvious over the prior art of record if rewritten. Amamiya discloses wherein the patterning surface and the voltage source are connected by a first current-limiting component, wherein the first current-limiting component comprises at least one of a resistor, an inductor, a diode, or a switch (Figs. 7, 9, abstract, pages 3-4 and 9-10 of the attached English translation, a switch (see Figs. 7a-b and 9a-c) is arranged between the voltage source and the patterning surface of the mask 1). Amamiya fails to describe or render obvious wherein the first current-limiting component is formed in the non-patterning surface of the patterning device outside a patterning area. Although Yamamoto (WO 2006/033442) discloses wherein an insulator is formed in the non-patterning surface of the patterning device outside a patterning area (Figs. 1-2, pages 6-7 of the 5/13/2026 English translation, the mask M includes a glass substrate 1 arranged on a non-patterning side of the film 2 and outside the absorber 4), Yamamoto fails to describe or suggest a first current-limiting component comprises at least one of a resistor, an inductor, a diode, or a switch arranged in the non-patterning surface of the patterning device outside a patterning area. Response to Arguments Applicant’s arguments, see page 9, filed 8/10/2026, with respect to the objections to claims 75-77 and 88 have been fully considered and are persuasive in light of the amendments to the claims. The objections to claims 75-77 and 88 have been withdrawn. Applicant’s arguments, see page 10, filed 8/10/2026, with respect to the 35 U.S.C. 112(f) interpretation of the language “a first current-limiting component” in claim 73 have been fully considered and are persuasive owing to the amendment to claim 73. The 35 U.S.C. 112(f) interpretation of the language “a first current-limiting component” in claim 73 has been withdrawn. Applicant’s arguments, see pages 10-11, filed 8/10/2026, with respect to the 35 U.S.C. 112(b) rejections of claims 74-76, 78, 80, and 88 have been fully considered and are persuasive owing to the amendments to the claims. The 35 U.S.C. 112(b) rejections of claims 74-76, 78, 80, and 88 have been withdrawn. Applicant’s arguments, see page 11, filed 8/10/2026, with respect to the 35 U.S.C. 112(d) rejections of claim 84 have been fully considered and are persuasive owing to the cancellation of claim 84. The 35 U.S.C. 112(d) rejection of claim 84 has been withdrawn. Applicant's arguments filed 8/10/2026 have been fully considered but they are not persuasive. Applicant argues on pages 11-13 that Kim fails to disclose “wherein the voltage source is configured to apply the voltage to the patterning surface to reduce positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface” as recited in claim 69. The Applicant alleges that the claim language requires “to reduce positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface,” that Kim fails to teach photoelectron emission and instead teaches applying treatment to resolve a different charging mechanism from ionized hydrogen. Applicant alleges claim 69 is “directed to the charge state of the patterning surface, not merely the charge state of the contaminant particles, as required by Kim” and alleges that Kim at best describes applying voltage to a reticle surface to repel negatively charged particles. The Examiner respectfully disagrees. Under the broadest reasonable interpretation of apparatus claim 69 as drafted, Kim discloses wherein the voltage source is configured to apply the voltage to the patterning surface to reduce positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface (the limitation “wherein the voltage source is configured to apply the voltage to the patterning surface to reduce positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface” is functional language that recites the manner of operating the device and does not differentiate the claimed apparatus from the structure as taught by Kim. See MPEP 2114. Figs. 1-15, 17, paras. [0032], [0039]-[0042], [0046]-[0047], [0052]-[0054], [0056]-[0065], [0068]-[0069], [0074], [0080]-[0091], [0096], [0101]-[0110], a reticle stage power source 300 or voltage sources 1-3 applies voltage to the first surface 210a on which the pattern region 215 is formed). The claim recites “a patterning device voltage biasing system for use in a lithographic apparatus, the patterning device voltage biasing system comprising…wherein the voltage source is configured to apply the voltage to the patterning surface to reduce positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface.” The apparatus claim 69 does not positively recite a lithographic apparatus producing radiation incident on the patterning surface, and the language “to reduce positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface” is functional language that describes the intended operation of the voltage source in the patterning device voltage biasing system. “‘[A]pparatus claims cover what a device is, not what a device does.’ Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a ‘recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus’ if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).” MPEP 2114. The language “wherein the voltage source is configured to apply the voltage to the patterning surface to reduce positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface” does not recite structural limitations for the voltage source or the patterning device voltage biasing system as a whole, and Kim discloses the reticle stage power source or voltage source may apply negative voltage to the pattern surface of the reticle (at least paras. [0046]-[0047], [0061]-[0064], [0096], [0102]-[0103]). Kim discloses the structural elements of the patterning device voltage biasing system as recited, and therefore Kim discloses a patterning device configured to impart a pattern to a beam of radiation, the patterning device comprising a patterning surface with a pattern thereon (Figs. 1-15, 17, paras. [0008]-[0009], [0030], [0032], [0036], [0039]-[0040], [0135], reticle 210 includes a pattern region 215 formed on the first surface 210a that patterns exposure light projected to a wafer); and a voltage source (Figs. 1-15, 17, paras. [0032], [0046]-[0047], [0053]-[0054], [0056]-[0065], [0080]-[0091], [0096], [0101]-[0110], a reticle stage power source 300 or voltage sources 1-3), wherein the patterning device voltage biasing system is configured such that a voltage is applied to the patterning surface of the patterning device by the voltage source (Figs. 1-15, 17, paras. [0032], [0039]-[0042], [0046]-[0047], [0052]-[0054], [0056]-[0065], [0068]-[0069], [0074], [0080]-[0091], [0096], [0101]-[0110], a reticle stage power source 300 or voltage sources 1-3 applies voltage to the first surface 210a on which the pattern region 215 is formed), and wherein the voltage source is configured to apply the voltage to the patterning surface to reduce positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface (the limitation “wherein the voltage source is configured to apply the voltage to the patterning surface to reduce positive charging of the patterning surface resulting from photoelectron emission caused by radiation incident on the patterning surface” is functional language that recites the manner of operating the device and does not differentiate the claimed apparatus from the structure as taught by Kim. See MPEP 2114. Figs. 1-15, 17, paras. [0032], [0039]-[0042], [0046]-[0047], [0052]-[0054], [0056]-[0065], [0068]-[0069], [0074], [0080]-[0091], [0096], [0101]-[0110], a reticle stage power source 300 or voltage sources 1-3 applies voltage to the first surface 210a on which the pattern region 215 is formed). Applicant’s arguments have been fully considered, but they are not persuasive. Applicant’s arguments with respect to claims 73, 74, 82, 83, 85-88 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINA A. RIDDLE whose telephone number is (571)270-7538. The examiner can normally be reached M-Th 6:30AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Minh-Toan Ton can be reached at (571)272-2303. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINA A RIDDLE/Primary Examiner, Art Unit 2882
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Prosecution Timeline

Dec 16, 2024
Application Filed
May 13, 2026
Non-Final Rejection mailed — §102, §103
Aug 10, 2026
Response Filed
Oct 15, 2026
Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
95%
With Interview (+14.0%)
2y 11m (~1y 1m remaining)
Median Time to Grant
Moderate
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