Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
1. Applicant’s arguments, filed January 20th, 2026, with respect to the rejection of the independent claims under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive in light of the claim amendments. Therefore, the rejection has been withdrawn. However, upon further consideration, new grounds of rejection are made in view of Nakajima (US 2007/0074010).
Applicant’s argument that the table described by Jackson, cited in the previous Office Action, is different from the table of the amended claims is considered persuasive due to the arguments’ clarification that the recited table includes the full machine-language instruction itself, not just a reference, description, or address of the instruction, is considered persuasive. While a table that “describes” a machine-language instruction would normally be interpreted as simply including the address of said instruction as its description, Applicant’s arguments have narrowed the correct interpretation of the claim to merely include a table that includes the instruction itself, as argued on page 8 of the Remarks.
Applicant’s argument regarding the “pipeline controller” is not considered persuasive, as the argument relies upon alleged features of the invention not found within the language of the claims to distinguish the claims from the previously cited prior art. Applicant argues that the disclosure of Jackson “does not rewrite the value of the program counter” and “never controls the pipeline processing to avoid the occurrence of pipeline bubbles”, but these features are not recited within the language of the independent claims. The claims merely require that “a pipeline controller” is “configured to set…an address…into the program counter”, which is disclosed in at least paragraphs [0037], [0054], and [0063] of Jackson, as previously cited. The argument is therefore not considered persuasive with respect to the “pipeline controller”.
Claim Objections
2. Claims 1 and 5-10 are objected to because of the following informalities:
In claims 1, 5, and 6, all occurrences of the phrases “the destination of jump” should be replaced with “the destination of the jump” for clarity and proper grammar.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1 and 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Jackson (US 2014/0201509, cited in the IDS dated August 15th, 2025) and Nakajima (US 2007/0074010, cited in the IDS dated December 19th, 2024).
Regarding claim 1, Jackson teaches a processor configured an instruction fetcher configured to fetch a machine-language instruction based on a memory address set in a program counter ([0041], fetch stage 102);
a decoder configured to decode the machine-language instruction output from the instruction fetcher into a control information ([0041], decode and renaming stage 104); and
an executer configured to execute the control information output from the decoder, and execute pipeline processing ([0042], execution pipelines), the processor further comprising:
a table configured to describe, for each destination of a jump, a head address of a code at the destination of jump, a second machine-language instruction, and a control information of a head machine-language instruction ([0051], [0054], tagged jump tables with multiple entries); and
a pipeline controller configured to set, when the executer executing a control information of a jump, an address specifying a second machine-language instruction at a destination of the jump into the program counter by using the table, while to input a head machine-language instruction at the destination of the jump to the decoder ([0051-0054], jump table entries including destination information),
the processor being manufactured by being described using a source code written in a hardware description language ([0013], HDL),
the table being created when linking a machine-language instruction of a code of a source of a jump and a machine-language instruction of a code of a destination of the jump ([0060-0063], create table entry based on initial detection of switch statement instruction to store source address and predicted target location).
Jackson fails to teach wherein the table describes the head machine-language instruction of the code at the destination of the jump.
Nakajima teaches a processor comprising a table to describe a machine-language instruction of code at a destination of a jump (claim 12, [0075-0088], jump destination instruction storage unit to hold addresses of and instructions at the destination of jumps).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Jackson and Nakajima to allow for the jump table of Jackson to include the instruction code held at the jump destination target address. While Jackson describes the exemplary table holding the instruction identification tag (address) for targets of jump instructions, Nakajima discloses storage of both the address and instruction at a jump destination. This allows for the processor to immediately begin execution at the jump destination using the stored instruction, as described by Nakajima, increasing the efficiency of the processor. As both references disclose the use of storage structures for holding jump destination instruction information, the combination would merely entail the simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 5, Jackson teaches a processor configured to comprise:
an instruction fetcher configured to fetch a machine-language instruction based on a memory address set in a program counter ([0041], fetch stage 102);
a decoder configured to decode the machine-language instruction output from the instruction fetcher into a control information ([0041], decode and renaming stage 104); and
an executer configured to execute the control information output from the decoder, and execute pipeline processing ([0042], execution pipelines), the processor further comprising:
a table configured to describe, for each destination of jump, a head address of a code at the destination of jump and a head machine-language instruction ([0051], [0054], tagged jump tables with multiple entries); and
a pipeline controller configured to set, when the executer is executing a control information of a jump, an address specifying a second machine-language instruction of a code at a destination of the jump into the program counter by using the table, while to input a head machine-language instruction of the code at the destination of the jump to the decoder by using the table ([0051-0054], jump table entries including destination information),
the processor being manufactured by being described using a source code written in a hardware description language ([0013], HDL),
a label for a destination of a jump, and a head machine-language instruction at the destination of the jump being described at a code of a source of the jump ([0051-0054], jump table entries),
for each label for a destination of a jump, a head address and a head machine-language instruction of a code at the destination of the jump being described in the table ([0042], [0051-0054], [0085], jump table entries & target prediction), and
the table being created using only a code at source of a jump without referring to a code at destination of the jump ([0051-0054], [0085], predicting destination without knowing or referring to target address).
Jackson fails to teach wherein the table describes the head machine-language instruction of the code at the destination of the jump.
Nakajima teaches a processor comprising a table to describe a machine-language instruction of code at a destination of a jump (claim 12, [0075-0088], jump destination instruction storage unit to hold addresses of and instructions at the destination of jumps).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Jackson and Nakajima to allow for the jump table of Jackson to include the instruction code held at the jump destination target address. While Jackson describes the exemplary table holding the instruction identification tag (address) for targets of jump instructions, Nakajima discloses storage of both the address and instruction at a jump destination. This allows for the processor to immediately begin execution at the jump destination using the stored instruction, as described by Nakajima, increasing the efficiency of the processor. As both references disclose the use of storage structures for holding jump destination instruction information, the combination would merely entail the simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 6, Jackson teaches a processor configured to comprise:
an instruction fetcher configured to fetch a machine-language instruction based on a memory address set in a program counter ([0041], fetch stage 102);
a decoder configured to decode the machine-language instruction output from the instruction fetcher into a control information ([0041], decode and renaming stage 104); and
an executer configured to execute the control information output from the decoder, and execute pipeline processing ([0042], execution pipelines), the processor further comprising:
a table configured to describe, for each destination of jump, a head address of a code at the destination of jump, a second machine-language instruction, and a control information of a head machine-language instruction of the code at the destination of jump ([0051], [0054], tagged jump tables with multiple entries); and
a pipeline controller configured to set, when the executer is executing a control information of a jump, an address specifying a third machine-language instruction of a code at a destination of the jump into the program counter by using the table, while to input a second machine-language instruction of a code at the destination of the jump to the decoder and to input a control information of a head machine-language instruction of the code at the destination of the jump to the executer by using the table ([0051-0054], jump table entries including destination information).
Jackson fails to teach wherein the table describes the head machine-language instruction of the code at the destination of the jump.
Nakajima teaches a processor comprising a table to describe a machine-language instruction of code at a destination of a jump (claim 12, [0075-0088], jump destination instruction storage unit to hold addresses of and instructions at the destination of jumps).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Jackson and Nakajima to allow for the jump table of Jackson to include the instruction code held at the jump destination target address. While Jackson describes the exemplary table holding the instruction identification tag (address) for targets of jump instructions, Nakajima discloses storage of both the address and instruction at a jump destination. This allows for the processor to immediately begin execution at the jump destination using the stored instruction, as described by Nakajima, increasing the efficiency of the processor. As both references disclose the use of storage structures for holding jump destination instruction information, the combination would merely entail the simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 7, the combination of Jackson and Nakajima teaches the processor as claimed in claim 6, wherein, after the pipeline controller performs processing, the executer executes the control information of the head machine-language instruction of the code at the destination of the jump in accordance with a first clock, while the decoder decodes the second machine-language instruction of the code at the destination of the jump into a control information, and the instruction fetcher fetches the third machine-language instruction of the code at the destination of the jump in accordance with the first clock (Jackson [0051-0054], [0085-0086], predicting and fetching at target of jump instruction).
Regarding claim 8, the combination of Jackson and Nakajima teaches the processor as claimed in claim 7, wherein the instruction fetcher, the decoder, and the executer execute a plurality of consecutive machine-language instructions in parallel in synchronization with clock, the processor further comprising: a first buffer configured to temporarily store a machine-language instruction output from the instruction fetcher in accordance with a first clock and then input the machine-language instruction to the decoder in accordance with a second clock; and a second buffer configured to temporarily store a control information output from the decoder in accordance with the first clock and then input the control information to the executer in accordance with the second clock, and wherein the pipeline controller sets the second machine-language instruction of the code at the destination of the jump into the first buffer and sets the control information of the head machine-language instruction of the code at the destination of the jump into the second buffer (Jackson [0011], parallel processing, [0041], fetch & decode, [0042], reorder buffer to maintain instructions, [0051-0054], predicting and fetching from target of jump instructions).
Regarding claim 9, the combination of Jackson and Nakajima teaches the processor as claimed in claim 6, wherein the processor is manufactured by being described using a source code written in a hardware description language (Jackson [0013], HDL),
the table being created when linking a machine-language instruction of a code at source of a jump and a machine-language instruction of a code at destination of the jump (Jackson [0060-0063], create table entry based on initial detection of switch statement instruction to store source address and predicted target location).
Regarding claim 10, the combination of Jackson and Nakajima teaches the processor as claimed in claim 6, wherein the processor is manufactured by being described using a source code written in a hardware description language (Jackson [0013], HDL),
wherein a label for a destination of a jump, a head machine-language instruction at the destination of the jump, and a second machine-language instruction at the destination of the jump are described at a code of a source of the jump (Jackson [0051-0054], jump table entries & Nakajima [0082], subsequent instructions),
wherein, for each label for a destination of a jump, a second machine-language instruction of a code at the destination of the jump, and a control information as a result of converting a head machine-language instruction of the code at the destination of the jump are described in the table (Jackson [0042], [0051-0054], [0085], jump table entries & target prediction & Nakajima [0082], subsequent instructions), and
wherein the table being created using only a code at source of a jump without referring to a code at destination of the jump (Jackson [0051-0054], [0085], predicting destination without knowing or referring to target address).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183