Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 7-16, 18, and 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang (2020/0273664).
Regarding claim 1, Wang discloses a substrate for a charged-particle detector, the substrate comprising: a charge sensing element formed on a first surface of the substrate and configured to detect charged particles originating from a sample (Wang, [0093], sensing element 711); and a plurality of transistors formed in a first region of a second surface of the substrate (Wang, [0094], gain element 721; [0128] indicating an array thereof), the second surface being opposite the first surface, wherein a top surface of each transistor of the plurality of transistors is coplanar with a top surface of the first region and with the second surface of the substrate (Wang, Fig. 7, note relative positions of 711 and the constituent components of 721).
Regarding claim 2, Wang further discloses the charge sensing element comprises a diode, a photodiode, a single-photon avalanche diode, or an avalanche photodiode. (Wang, [0093])
Regarding claim 4, Wang further discloses the first region comprises a p-type well formed inside the substrate such that a top surface of the p-type well is coplanar with the second surface of the substrate. (Wang, Fig. 11F, p++ region 745, [0138])
Regarding claim 7, Wang further discloses the second surface is downstream from the first surface with respect to a path of the charged particles. (Wang, Fig. 12, charged particle incidence side shown with arrow)
Regarding claim 8, Wang further discloses wherein the second surface comprises a substantially topology-less surface. (Wang, Fig. 12, second surface substantially flat)
Regarding claim 9, Wang further discloses transistors of the plurality of transistors are isolated from each other by junction isolation. (Wang, Figs. 8A, 8B)
Regarding claim 10, Wang further discloses transistors of the plurality of transistors are isolated from each other without a dielectric material or a shallow trench isolation (STI). (Wang, Figs. 8A, 8B)
Regarding claim 11, Wang discloses a charged-particle beam apparatus, comprising: a charged-particle source configured to emit primary charged particles to be incident on a sample; anda charged-particle detector configured to detect secondary charged particles generated from the sample upon interaction with the primary charged particles (Wang, Fig. 2), the charged-particle detector comprising: a substrate layer comprising a first surface and a second surface opposite the first surface; a charge sensing element formed on the first surface and configured to detect charged particles originating from a sample; and a plurality of transistors formed in a first region of the second surface of the substrate layer, wherein a top surface of each transistor of the plurality of transistors is coplanar with a top surface of the first region and with the second surface of the substrate layer. (Wang, Fig. 8A, 8B)
Regarding claim 15, Wang discloses a method for fabricating a substrate of a charged-particle detector, the method comprising: forming a charge sensing element on a first surface of the substrate, the charge sensing element configured to detect charged particles originating from a sample; forming a plurality of transistors in a first region of a second surface of the substrate, the second surface being opposite the first surface, wherein a top surface of each transistor of the plurality of transistors is coplanar with a top surface of the first region and with the second surface of the substrate. (Wang, Figs. 8A, 8B; see also construction steps 11A-11I, note that unless particularly specified method steps need not be performed in order)
Regarding claim 16, Wang further discloses the charge sensing element comprises a diode, a photodiode, a single-photon avalanche diode, or an avalanche photodiode. (Wang, [0093])
Regarding claim 18, Wang further discloses the first region comprises a p-type well formed inside the substrate such that a top surface of the p-type well is coplanar with the second surface of the substrate layer. (Wang, Fig. 11F, p++ region 745, [0138])
Regarding claim 21, Wang further discloses the second surface is downstream from the first surface with respect to a path of the charged particles. (Wang, Fig. 12, charged particle incidence side shown with arrow)
Regarding claim 22, Wang further discloses transistors of the plurality of transistors are isolated from each other by junction isolation. (Wang, Figs. 8A, 8B)
Regarding claim 23, Wang further discloses transistors of the plurality of transistors are isolated from each other without a dielectric or a shallow trench isolation (STI). (Wang, Figs. 8A, 8B)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Leifso et al. (2003/0193355)
Regarding claims 3 and 17, CMOS technology (including NMOS and PMOS types) is a known equivalent to the BJT technology disclosed in Wang. (Leifso, [0052])
It would have been obvious to one of ordinary skill in the art before the filing date of the claimed invention to use CMOS technology (of either type) to form the transistors of Wang as the substitution of one art-recognized-equivalent for another.
Claims 5, 6, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Park et al. (KR 2009 0025944 A)
Regarding claims 5, 6, 19, and 20, Wang lacks explicit teaching of a conductive isolation will and its construction details.
Park teaches the use of conductive isolation wells to separate the pixels in an imaging detector. (Park, text description of Fig. 5, “A second conductive isolation well 108 may be formed below the device isolation region 109 to define each pixel unit of the image sensor.”)
It would have been obvious to one of ordinary skill in the art before the filing date of the claimed invention to use the conductive isolation well of Park to separate the pixels of Wang.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWIN C GUNBERG whose telephone number is (571)270-3107. The examiner can normally be reached Monday-Friday, 8:30AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uzma Alam can be reached at 571-272-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EDWIN C GUNBERG/Primary Examiner, Art Unit 2884
Prosecution Insights