CTNF 18/881,494 CTNF 100241 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION This action is responsive to the Application filed January 6, 2025. Status of claims to be treated in this office action: a. Independent: 1 b. Pending: 1-7 Claim 1 has been amended through preliminary amendments. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. 06-11-01 AIA The following title is suggested: A semiconductor device with stacked cell array and reading circuit layers . The disclosure is objected to because of the following informality: On page 10, para. [0044], line 16, make the following change: “In an OS transistor, a current that flows between a source and a drain is in an off state” Appropriate correction is required . Claim Objections Claim 1 is objected to because of the following informality: Regarding claim 1, make the following change: “wherein the second element layer is positioned over and overlap overlaps with the first element layer,” Appropriate correction is required. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-4 and 11-13 are rejected under 35 U.S.C. 102( a)(1) and 102(a)(2 ) as being anticipated by Shin et al. (US Pub. US 20190096453 A1; “Shin”) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US Pub. US 20190096453 A1; “Shin”) in view of Toda (US Pub. 20060197115 A1) . Regarding independent claim 1, Shin discloses semiconductor device (Fig. 2: system 10; [0030]) comprising: an arithmetic device (host device 2000; [0031]) ; a bus wiring (interconnect device 12; [0034]) ; and a memory device (stacked memory device 1000; [0031]) , wherein the memory device comprises a first element layer comprising a plurality of reading circuits (logic semiconductor die 1010; [0032]; in reference to Fig. 7, per [0065]: during normal read and write operations, data may be exchanged between the logic semiconductor die 1010 and the first memory semiconductor die 1100. Examiner concludes that the logic semiconductor die includes reading circuits) and a second element layer comprising a plurality of cell arrays (memory semiconductor die 1070; [0032]) , a sense amplifier (Fig. 4: bit line sense amplifiers BLSA; [0043]; [0042]: [0042] FIG. 4 is a diagram illustrating a memory bank included in the stacked memory device of FIG. 2) , wherein the cell arrays each comprise a memory cell ([0043]: Each data block may include a plurality of sub memory cell arrays SARR and each sub memory cell array SARR may include a plurality of memory cell) , wherein the second element layer is positioned over and overlap with the first element layer ([0032]: the memory semiconductor dies 1070 and 1080 are vertically stacked with the logic semiconductor die 1010) , wherein the memory cell and the sense amplifier are electrically connected to each other through a bit line, ([0043]: In a read operation, bit line sense amplifiers BLSA may sense and amplify data stored in the memory cells to sequentially provide the read data to the outside of the memory bank (e.g., an external device) via local input-output lines LIO and global input-output lines GIO) wherein the memory device is electrically connected to the arithmetic device through the bus wiring ([0034]: The memory interface 1020 may perform communication with an external device such as the host device 2000 through an interconnect device 12; also see Fig. 2) , and wherein data retained in one of the plurality of cell arrays is output to the bus wiring through one of the plurality of reading circuits ([0065]; [0034]; [0043]) . Shin does not explicitly disclose: a first element layer comprising a plurality of reading circuits And Shin does not disclose: wherein the reading circuits each comprise a sense amplifier, However, Toda teaches: a first element layer (Fig. 6: read/write circuit 200; [0053]) comprising a plurality of reading circuits ([0058]: sense amplifier arrays 203 and 204) wherein the reading circuits each comprise a sense amplifier ([0058]: sense amplifiers in the sense amplifier arrays 203 and 204) , It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Toda to Shin wherein the device comprises a first element layer comprising a plurality of reading circuits, and wherein the reading circuits each comprise a sense amplifier in order to increase the memory capacity and achieve high-speed access in a large capacitive memory (Toda, [0064]). Regarding claim 2, Shin and Toda together disclose the limitations of claim 1, and further through Shin: wherein the data output to the bus wiring is output with a bit width that is a multiple of 8 bits ([0109]: For example, if the data bus corresponding to the one calculation semiconductor die has a data width of 128 bits) . 07-22-aia AIA Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Shin (US Pub. US 20190096453 A1) in view of Toda (US Pub. 20060197115 A1) as applied to claim 1 above, and further in view of Hodo et al. (US Pub. 20200279951 A1; “Hodo”) . Regarding claim 3, Shin and Toda together disclose the limitations of claim 1, and further through Shin: wherein the first element layer comprises an input/output circuit (Fig. 2: memory interface MIF 1020; [0033]-[0034]) , and Neither Shin nor Toda discloses: wherein the input/output circuit comprises a plurality of interface circuits. However, Hodo teaches: wherein the input/output circuit (Fig. 23A: input/output blocks (IOBs) 3117; [0331]) comprises a plurality of interface circuits ([0331]: The IOB 3117 includes a plurality of programmable input/output circuits) . It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Hodo to modified Shin wherein the input/output circuit comprises a plurality of interface circuits in order to implement a semiconductor device with high reliability, favorable electrical characteristics, and long data retention (Hodo, [0010]) . 07-22-aia AIA Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Shin (US Pub. US 20190096453 A1) in view of Toda (US Pub. 20060197115 A1) as applied to claim 1 above, and further in view of Park et al. (US Pub. 20160049197 A1; “Park”) . Regarding claim 4, Shin and Toda together disclose the limitations of claim 1. Neither Shin nor Toda discloses: wherein the reading circuits each comprise a precharge circuit. However, Park teaches: wherein the reading circuits (Fig. 12A: write/read circuits WD/SA1, WD/SA2, and WD/SA3; [0113]: As illustrated in FIG. 12A, the control layer may include various circuits such as a power generating unit that generates power and multiple write/read circuits WD/SA1, WD/SA2, and WD/SA3) each comprise a precharge circuit ([0060]: The write/read circuit 123 may include a write driver WD and a sense amp SA) . It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Park to modified Shin wherein the reading circuits each comprise a precharge circuit in order to use a stacking architecture to decrease the total size of the memory device (Park, [0085]) . 07-22-aia AIA Claim s 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Shin (US Pub. US 20190096453 A1) in view of Toda (US Pub. 20060197115 A1) as applied to claim 1 above, and further in view of Yamazaki et al. (US Pub. 20200365592 A1; “Yamazaki”) . Regarding claim 5, Shin and Toda together disclose the limitations of claim 1. Shin discloses a first and second element layer. Neither Shin nor Toda discloses: a first transistor in which a first semiconductor layer comprising a channel formation region comprises silicon, and a second transistor in which a second semiconductor layer comprising a channel formation region comprises an oxide semiconductor. However, Yamazaki teaches: a first transistor in which a first semiconductor layer comprising a channel formation region comprises silicon (claim 2: a semiconductor material of a semiconductor layer of the first transistor and a semiconductor material of a semiconductor layer of the third transistor comprise silicon) , and a second transistor in which a second semiconductor layer comprising a channel formation region comprises an oxide semiconductor (claim 2: a semiconductor material of a semiconductor layer of the second transistor comprises an oxide semiconductor comprising In, Ga, and Zn) . It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Yamazaki to modified Shin wherein the memory device comprises a first transistor in which a first semiconductor layer comprising a channel formation region comprises silicon, and a second transistor in which a second semiconductor layer comprising a channel formation region comprises an oxide semiconductor in order to provide a novel structure for a semiconductor memory device which retains data regardless of power supply and does not experience a limit on writing operations due to the deterioration of a gate insulating layer (Yamazaki, [0008] & [0011]). Regarding claim 6, Shin, Toda, and Yamazaki together disclose the limitations of claim 5, and further through Yamazaki: wherein the oxide semiconductor comprises In, Ga, and Zn (claim 2: a semiconductor material of a semiconductor layer of the second transistor comprises an oxide semiconductor comprising In, Ga, and Zn) . It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Yamazaki to modified Shin wherein the oxide semiconductor comprises In, Ga, and Zn in order to provide a novel structure for a semiconductor memory device which retains data regardless of power supply and does not experience a limit on writing operations due to the deterioration of a gate insulating layer (Yamazaki, [0008] & [0011]) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 07-96 The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Itagaki (US Pub. 20140269073 A1): paras. [0106]-[0107] and Fig. 14 are relevant to claim 1. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH ROSE AGGER whose telephone number is (571)270-0250. The examiner can normally be reached Mon-Fri, 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rich Elms can be reached at 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /E.R.A./Examiner, Art Unit 2824 /HAN YANG/Primary Examiner, Art Unit 2824 6/13/2026 Application/Control Number: 18/881,494 Page 2 Art Unit: 2824 Application/Control Number: 18/881,494 Page 3 Art Unit: 2824 Application/Control Number: 18/881,494 Page 4 Art Unit: 2824 Application/Control Number: 18/881,494 Page 5 Art Unit: 2824 Application/Control Number: 18/881,494 Page 6 Art Unit: 2824 Application/Control Number: 18/881,494 Page 7 Art Unit: 2824 Application/Control Number: 18/881,494 Page 8 Art Unit: 2824 Application/Control Number: 18/881,494 Page 9 Art Unit: 2824 Application/Control Number: 18/881,494 Page 10 Art Unit: 2824
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