Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 11, 2024 was filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
--Semiconductor Device Comprising A Spacer Structure Including First And Second Segments--
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-10 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-9 of U.S. Patent No. US 12,127,392, hereinafter the Prior Patent, in view of Kim et al. (U.S. Pub. 2021/0210493), hereinafter Kim.
Claim 1 of Instant Application
Claim 1 of Prior Patent
A semiconductor device, comprising:
a substrate;
a bit line structure formed over and protruding from the substrate; a spacer structure formed on and extending along sidewall of the bit line structure, wherein the spacer structure includes: a first segment near a top of the spacer structure with a slope, and
a second segment beneath the first segment, consisting of the first spacer layer contacting the bit line structure, a second spacer layer contacting the first spacer layer, and the third spacer layer contacting the second spacer layer,
wherein the second segment is capped with the first segment; and
a landing pad disposed on the bit line structure and covering the slope.
A semiconductor device, comprising:
a substrate;
a bit line structure formed over and protruding from the substrate; a spacer structure formed on and extending along sidewall of the bit line structure, wherein the spacer structure includes: a first segment near a top of the spacer structure with a slope; and
a second segment beneath the first segment, comprising a 3-layer structure,
(Within a spacer 3-layer structure, which is located on and extending along sidewall of the bit line structure, there is necessarily a layer identified as first spacer layer contacting the bit line structure. Similarly, in order to have a 3-layer structure, there must be a second spacer layer contacting the first spacer layer, and the third spacer layer contacting the second spacer layer)
wherein the second segment is capped with the first segment; and
a landing pad disposed on the bit line structure and covering the slope,
Claim 1 of Prior Patent does not explicitly define the structure such that:
[a first segment] consisting of a first spacer layer contacting the bit line structure and a third spacer layer contacting the first spacer layer;
Kim discloses a semiconductor device ((1); Figs. 11A-11D, Paragraph [0020]) comprising a substrate ((110); Fig. 11A, Paragraph [0023]); a bit line structure ((140) comprising (147) and (148); Fig. 11A, Paragraph [0043]) formed over and protruding from the substrate (110); a spacer structure ((150); Fig. 11A, Paragraph [0049]) formed on and extending along sidewall of the bit line structure (140), wherein the spacer structure includes: a first segment (e.g. portion of (150) with slope, ‘first segment’), wherein the first segment (‘first segment’) consists of:
- a first spacer layer ((152); Fig. 11A, Paragraph [0047]) contacting the bit line structure (140) and a third spacer layer ((158); Fig. 11A, Paragraph [0047]) contacting the first spacer layer (152).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kim into the claimed device of Claim 1 of Prior Patent such that the spacer structure includes a first segment consisting of a first spacer layer contacting the bit line structure and a third spacer layer contacting the first spacer layer. This would be due to the fact that doing so would produce the predictable result of incorporating a viable spacer structure composition into a device configured for DRAM operations.
Claim 2 of Instant Application
Claim 2 of Prior Patent As Modified By Kim
The semiconductor device of claim 1,
wherein the first spacer layer, the second spacer layer and the third spacer layer of the second segment are formed as a 3-layer structure,
and the 3-layer structure comprises at least two different materials.
The semiconductor device of claim 1,
[a second segment beneath the first segment, comprising a 3-layer structure,]
(As identified in the Claim 1 rejection above above)
wherein the 3-layer structure comprises at least two different materials.
Claim 3 of Instant Application
Claim 3 of Prior Patent As Modified By Kim
The semiconductor device of claim 2,
wherein the 3-layer structure comprises an oxide layer in the middle thereof.
The semiconductor device of claim 2,
wherein the 3-layer structure comprises an oxide layer in the middle thereof.
Claim 4 of Instant Application
Claim 4 of Prior Patent As Modified By Kim
The semiconductor device of claim 2,
wherein the second spacer layer is an air gap.
The semiconductor device of claim 2,
wherein the 3-layer structure comprises an air gap in the middle thereof.
(Here, where the middle layer is identified as the second spacer layer, as in the rejection of Claim 1 above, the same limitation is present. See also Kim, Fig. 11A, Paragraphs [0095] and [0090]
Regarding Claim 5, Claim 4 of Prior Patent as modified by Kim does not teach:
-an insulating layer disposed on the air gap and overlying the landing pad and the bit line structure.
Kim further teaches:
-an insulating layer ((195); Fig. 11A, Paragraph [0111]) disposed on the air gap ((AS); Fig. 11A, Paragraph [0099]) and overlying the landing pad ((194); Fig. 11A, Paragraph [0069]) and the bit line structure (140).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kim into the claimed device of Claim 1 of Prior Patent such that it further comprises an insulating layer disposed on the air gap and overlying the landing pad and the bit line structure. This would be due to the fact that doing so would produce the predictable result of incorporating an in insulating material between adjacent landing pads, thereby defining individual bit connections (See also Kim, Paragraph [0108])
Claim 6 of Instant Application
Claim 5 of Prior Patent As Modified By Kim
The semiconductor device of claim 1,
wherein the first spacer layer and the third spacer layer of the first segment are formed as a 2-layer structure.
The semiconductor device of claim 1,
wherein the first segment comprises a 2-layer structure. (Wherein the first segment contains the first spacer layer and the third spacer layer, as in the rejection of Claim 1)
Claim 7 of Instant Application
Claim 6 of Prior Patent As Modified By Kim
The semiconductor device of claim 1,
wherein a width of the first segment is gradually decreased from an interface with the second segment to the top of the first segment.
The semiconductor device of claim 1,
wherein a width of the first segment is gradually decreased from an interface with the second segment to the top of the first segment.
Claim 8 of Instant Application
Claim 7 of Prior Patent As Modified By Kim
The semiconductor device of claim 1,
wherein a ratio of a width of a top of the first segment to a width of a top of the second segment is in a range between 20% and 50%.
The semiconductor device of claim 1,
wherein a ratio of a width of a top of the first segment to a width of a top of the second segment is in a range between 20% and 50%.
Claim 9 of Instant Application
Claim 8 of Prior Patent As Modified By Kim
The semiconductor device of claim 1,
wherein a difference between a width of a top of the first segment and a width of a top of the second segment is in a range between 5 nm and 8 nm.
The semiconductor device of claim 1,
wherein a difference between a width of a top of the first segment and a width of a top of the second segment is in a range between 5 nm and 8 nm.
Claim 10 of Instant Application
Claim 9 of Prior Patent As Modified By Kim
The semiconductor device of claim 1,
wherein a vertical length of the first segment is between 15 nm and 35 nm.
The semiconductor device of claim 1,
wherein a vertical length of the first segment is between 15 nm and 35 nm.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim.
Regarding Claim 1, Kim discloses a semiconductor device ((1); Figs. 11A-11D, Paragraph [0020]) comprising:
-a substrate ((110); Fig. 11A, Paragraph [0023]);
-a bit line structure ((140) comprising (147) and (148); Fig. 11A, Paragraph [0043]) formed over and protruding from the substrate (110);
-a spacer structure ((150); Fig. 11A, Paragraph [0049]) formed on and extending along sidewall of the bit line structure (140), wherein the spacer structure includes:
-a first segment near a top of the spacer structure with a slope (e.g. portion of (150) with slope, hereinafter ‘1S’), consisting of:
- a first spacer layer ((152); Fig. 11A, Paragraph [0047]) contacting the bit line structure (140) and a third spacer layer ((158); Fig. 11A, Paragraph [0047]) contacting the first spacer layer (152); and
-a second segment (e.g. portion of (150) without slope, hereinafter ‘2S’) beneath the first segment (1S), consisting of
-the first spacer layer (152) contacting the bit line structure (140), a second spacer layer ((154)/(AS); Figs. 11A and 8A, Paragraphs [0048] and [0099], Kim provides embodiments wherein the second spacer layer is either an oxide film or an air spacer) contacting the first spacer layer (152), and the third spacer layer ((158); Fig. 11A, Paragraph [0047]) contacting the second spacer layer ((154)/(AS)),
(Examiner notes “contacting” does not preclude intervening layers and further more Kim provides for an embodiment for the spacer structure wherein only elements (152), (154)/(AS), and (158) are present (i.e. no element (156)- See Paragraph [0047]))
wherein
-the second segment (2S) is capped with the first segment (1S); and
-a landing pad ((190); Fig. 11A, Paragraph [0069]) disposed on the bit line structure (140) and covering the slope (slope of (1S)).
Regarding Claim 2, Kim teaches the semiconductor device ((1); Figs. 11A-11D, Paragraph [0020]) of Claim 1, wherein:
-the first spacer layer (152), the second spacer layer ((154)/(AS)) and the third spacer layer (158) of the second segment (2S) are formed as a 3-layer structure (Paragraph [0047], hereinafter ‘3L’), and the 3-layer structure comprises at least two different materials (Paragraph [0048]).
Regarding Claim 3, Kim teaches the semiconductor device ((1); Figs. 11A-11D, Paragraph [0020]) of Claim 2, wherein:
-the 3-layer structure (3L) comprises an oxide layer in the middle thereof (i.e. (154)/(AS) is an oxide, Paragraph [0048].
Regarding Claim 4, Kim teaches the semiconductor device ((1); Figs. 11A-11D, Paragraph [0020]) of Claim 2, wherein:
-the second spacer layer is an air gap (i.e. (154/(AS) is an air gap, Paragraph [0099] .
Regarding Claim 5, Kim teaches the semiconductor device ((1); Figs. 11A-11D, Paragraph [0020]) of Claim 4, further comprising:
-an insulating layer ((195); Fig. 11A, Paragraph [0111]) disposed on the air gap ((AS); Fig. 11A, Paragraph [0099]) and overlying the landing pad ((194); Fig. 11A, Paragraph [0069]) and the bit line structure (140).
Regarding Claim 6, Kim teaches the semiconductor device ((1); Figs. 11A-11D, Paragraph [0020]) of Claim 1, wherein:
-the first spacer layer (152) and the third spacer layer (158) of the first segment (1S) are formed as a 2-layer structure (Paragraph [0047]).
(Examiner notes the two-layer structure may be a subset of the three-layer structure)
Regarding Claim 7, Kim teaches the semiconductor device ((1); Figs. 11A-11D, Paragraph [0020]) of Claim 1, wherein:
-a width (e.g. in the X-direction of Fig. 11A) of the first segment (1S) is gradually decreased from an interface with the second segment (2S) to the top of the first segment (top of (1S)) (i.e. along the Z-direction of Fig. 11A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Simsek-Ege et al. (U.S. Pub. 2020/0066729), hereinafter Simsek-Ege.
Regarding Claim 8, Kim teaches the semiconductor device ((1); Figs. 11A-11D, Paragraph [0020]) of Claim 1, upon which it depends, but fails to specifically disclose:
-a ratio of a width of a top of the first segment to a width of a top of the second segment is in a range between 20% and 50%.
Simsek-Ege teaches a semiconductor device ((100); Figs. 10, Paragraph [0020]) wherein:
-a ratio of a width of a top of the first segment segment (consisting of e.g. 4 nm (108) and 2 nm of (130)/(128); Fig. 10, Paragraphs [0025] and [0031]) to a width of a top of the second segment (consisting of e.g. 4nm of (110)/(148), 2 nm of (108), and 6 nm of (112); Paragraphs [0026] and [0027]) is in a range between 20% and 50% (in this case, 6 nm : 12 nm, a ratio of 50%).
Examiner notes Simsek-Ege provides a wide range of applicable thicknesses for the various layers that make up the spacer structure and the above cited dimensions are one example of viable width ratios between 20% to 50% to maintain desired electrical properties.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Simsek-Ege into the device of Kim such that a ratio of a width of a top of the first segment to a width of a top of the second segment is in a range between 20% and 50%. This would be due to the fact that doing so would produce the predictable result of incorporating a viable spacer structure dimensions into a device configured for DRAM operations.
Regarding Claim 9, Kim teaches the semiconductor device ((1); Figs. 11A-11D, Paragraph [0020]) of Claim 1, upon which it depends, but fails to specifically disclose:
-a difference between a width of a top of the first segment and a width of a top of the second segment is in a range between 5 nm and 8 nm.
Simsek-Ege teaches a semiconductor device ((100); Figs. 10, Paragraph [0020]) wherein:
-a difference between a width of a top of the first segment (consisting of e.g. 4 nm (108) and 2 nm of (130)/(128); Paragraphs [0025] and [0031]) and a width of a top of the second segment (consisting of e.g. 4nm of (110)/(148), 2 nm of (108), and 6 nm of (112); Paragraphs [0026] and [0027]) is in a range between 5 nm and 8 nm (effectively just difference of thickness of (112), i.e. 6nm).
Examiner notes Simsek-Ege provides a wide range of applicable thicknesses for the various layers that make up the spacer structure and the above cited dimensions are one example of viable widths to maintain desired electrical properties.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Simsek-Ege into the device of Kim such that a difference between a width of a top of the first segment and a width of a top of the second segment is in a range between 5 nm and 8 nm. This would be due to the fact that doing so would produce the predictable result of incorporating a viable spacer structure dimensions into a device configured for DRAM operations.
Regarding Claim 8, Kim teaches the semiconductor device ((1); Figs. 11A-11D, Paragraph [0020]) of Claim 1, upon which it depends, but fails to specifically disclose:
-a vertical length of the first segment is between 15 nm and 35 nm.
Simsek-Ege teaches a semiconductor device ((100); Figs. 10, Paragraph [0020]) wherein:
-a vertical length ((D2); Fig. 10, Paragraph [0029]) of the first segment (corresponding to portion of spacer structure curved in and above) is between 15 nm and 35 nm (e.g. 20 nm, Paragraph [0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Simsek-Ege into the device of Kim such that a vertical length of the first segment is between 15 nm and 35 nm. This would be due to the fact that doing so would produce the predictable result of incorporating a viable spacer structure dimensions into a device configured for DRAM operations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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/DMITRI MIHALIOV/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812
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