Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to CON application No. 18/883,482 filed on September 12, 2024.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS have been considered.
Double Patenting
5. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
6. Claims 1-4, 7-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-21 of U.S. Patent No. 12,101,971 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because each of the instant limitations are recited in or obvious from claims 1-21 of U.S. Patent No. 12,101,971 B2.
Regarding independent claim 1, Jeon et al. recites a display apparatus comprising:
a substrate comprising a main display area, a component area, and a peripheral area (claim 1, lines 1-3);
an auxiliary subpixel disposed over the component area (claim 1, line 8); and
an auxiliary pixel circuit disposed over the peripheral area (claim 1, line 9), and electrically connected to the auxiliary subpixel (claim 1, lines 12-13).
Regarding claim 2, Jeon et al. recites wherein, the auxiliary pixel circuit and the auxiliary subpixel are electrically connected through lines (claim 1, lines 12-13).
Regarding claim 3, Jeon et al. recites wherein, the lines comprise a metal connection line, a transparent connection line, and a connection line (claim 12, lines 1-3).
Regarding claim 4, Jeon et al. recites wherein, the metal connection line is disposed over the peripheral area (claim 9, lines 1-3).
Regarding claim 7, Jeon et al. recites wherein, one end of the connection line is electrically connected to the metal connection line through a first contact hole, and another end of the connection line is electrically connected to the transparent connection line through a second contact hole (claim 13, lines 1-5).
Regarding claim 8, Jeon et al. recites wherein, further comprising:
a first insulating layer disposed over the substrate (claim 1, line 4); and
a second insulating layer disposed over the first insulating layer and comprising an opening exposing at least a portion of the first insulating layer (claim 1, lines 5-7).
Regarding claim 9, Jeon et al. recites wherein, the first insulating layer and the second insulating layer comprise different materials, and the second insulating layer is disposed directly on the first insulating layer (claim 5, lines 1-4).
Regarding claim 10, Jeon et al. recites wherein, the first insulating layer comprises silicon oxide, and the second insulating layer comprises silicon nitride (claim 6, lines 1-3).
Regarding claim 11, Jeon et al. recites wherein, the transparent connection line is disposed directly on the first insulating layer (claim 3, lines 2-3).
Regarding claim 12, Jeon et al. recites wherein, the transparent connection line is disposed in the opening (claim 2, lines 1-2).
Regarding claim 13, Jeon et al. recites wherein, the opening overlaps the component area (claim 7, lines 1-2).
Regarding claim 14, Jeon et al. recites wherein, the opening overlaps at least a portion of the peripheral area (claim 8, lines 1-2).
Regarding claim 15, Jeon et al. recites wherein, the metal connection line is disposed directly on the second insulating layer (claim 11, lines 1-3).
Regarding claim 16, Jeon et al. recites wherein, further comprising:
a first organic insulating layer disposed over the first insulating layer (claim 10, lines 2-3); and
a second organic insulating layer disposed over the first organic insulating layer (claim 10, lines 4-5).
Regarding claim 17, Jeon et al. recites wherein, the connection line is disposed over the first organic insulating layer (claim 14, lines 1-3).
Regarding claim 18, Jeon et al. recites wherein, the metal connection line is disposed over the first organic insulating layer (claim 14, lines 1-3).
Regarding claim 19, Jeon et al. recites wherein, the metal connection line is disposed over the second organic insulating layer (claim 16, lines 1-3).
Regarding claim 20, Jeon et al. recites wherein, further comprising:
a main pixel circuit disposed over the main display area (claim 19, lines 2-4); and
a main subpixel disposed over the main display area and electrically connected to the main pixel circuit (claim 19, lines 5-6).
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
9. Claims 1-4, 20 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Choi et al. (US 2021/0193758 A1).
Regarding independent claim 1, Choi et al. teaches a display apparatus comprising (Fig. 7):
a substrate (121, para [0083]) comprising a main display area (AA1, para [0055]), a component area (AA2 buffer area, para [0078]), and a peripheral area (AA3 opaque area, para [0078]);
an auxiliary subpixel (buffer pixel, para [0078]) disposed over the component area (AA2); and
an auxiliary pixel circuit (pixel driving circuit, para [0080]) disposed over the peripheral area (AA3), and electrically connected to the auxiliary subpixel (buffer pixel).
Regarding claim 2, Choi et al. teaches wherein (Fig. 7), the auxiliary pixel circuit (pixel driving circuit) and the auxiliary subpixel (buffer pixel) are electrically connected through lines (OAN/BAN).
Regarding claim 3, Choi et al. teaches wherein (Fig. 7), the lines comprise a metal connection line (141 Ag), a transparent connection line (142), and a connection line (TEL).
Regarding claim 4, Choi et al. teaches wherein (Fig. 7), the metal connection line (141) is disposed over the peripheral area (AA3).
Regarding claim 20, Choi et al. teaches wherein (Fig. 7), further comprising:
a main pixel circuit (TELb) disposed over the main display area (AA1); and
a main subpixel (TOLED forming pixel) disposed over the main display area (AA1) and electrically connected to the main pixel circuit (TELb).
Allowable Subject Matter
10. Claims 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 5 recites wherein the transparent connection line is disposed over the component area and at least a portion of the transparent connection line is extended to the peripheral area.
Claim 6 recites wherein a light transmittance of the transparent connection line is higher than a light transmittance of the metal connection line.
Examiner’s Note
11. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
13. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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