DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5, 6,7, 8, & 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kirby (US Pub no 2022/0157728 A1) in view of Malladi US Pub no. 2022/0300426 A1).
Regarding claim 1, Kirby et al discloses An assembly structure(100c, [0024], fig. 1c), comprising: a substrate(130,[0020], fig. 1b/1c); an interconnection device(185,[0030], fig. 1c) disposed over and electrically connected to the substrate(130,[0030], fig. 1c);
a first memory controller device (105 of 100c, [0021], fig. 1c)disposed over and electrically connected to the substrate(130,[0021][0024], fig. 1c); a second memory controller device (105 of 100c, [0021][0024], fig. 1c)disposed over and electrically
connected to the substrate(130,[0024], fig. 1c), wherein the first memory controller device(105 of 100c,[ 0024], fig.1c) and the second memory controller device(105, 0024], fig. 1c) are disposed at different sides of the interconnection device(185,[0030], fig. 1c see 100c);
a logic device(160,[0030],fig. 1c) disposed over and electrically connected to the
interconnection device(185,[0030], fig. 1c), the first memory controller device(105, 0024], fig. 1c) and the second memory controller device(105, 0024], fig. 1c);
Kirby et al further teaches a first volatile memory(125,[0016-0017], fig. 1c) disposed over an electrically connected to the first memory controller (105 of 100c,[ 0024], fig.1c); and a second volatile memory device (125,[0016-0017], fig. 1c) disposed over and electrically connected to the second memory controller device(105 of 100c,[ 0024], fig.1c) but fails to teach a first non-volatile memory device disposed over and electrically connected to the first memory controller device; a first volatile memory device disposed side by side with the first non-volatile memory device, and disposed over and electrically connected to the first memory controller device; a second non-volatile memory device disposed over and electrically connected to the second memory controller device; and a second volatile memory device disposed side by side with the second non-volatile memory device, and disposed over and electrically connected to the second memory controller device.
However, Malladi et al discloses a non-volatile memory dies(226,[0041][0044], fig. 2) integrated with HBM dies(222,[0041][0044], fig. 2) on a controller die (220,[0041][0044][0047], fig. 2). It would have been obvious to one of ordinary skill in the art before the effective filing date to populate the memory controllers of Kirby et al with the with the non-volatile and volatile memory of Malladi et al such that a first non-volatile memory device disposed over and electrically connected to the first memory controller device; a first volatile memory device disposed side by side with the first non-volatile memory device, and disposed over and electrically connected to the first memory controller device; a second non-volatile memory device disposed over and electrically connected to the second memory controller device; and a second volatile memory device disposed side by side with the second non-volatile memory device, and disposed over and electrically connected to the second memory controller device results
to increase memory capacity to scale storage performance.
Regarding claim 5, Kirby et al discloses wherein the
interconnection device(185,[0030], fig. 1c) is entirely disposed within a projection of the
logic device(160,[0024], fig. 1c) in a vertical direction.
Regarding claim 6, Kirby et al discloses wherein the logic device (160,[0024], fig. 1c) overlaps the first memory controller device(105 of 100c,[0024], fig.1c), and the second memory controller device(105 of 100c,[ 0024], fig.1c) in a vertical direction fig. 1c.
Regarding claim 7, Kirby et al discloses memory device(125,[0016-0017], fig. 1c) disposed within a projection of the first memory controller device(105 of 100c,[ 0024], fig.1c) in a vertical direction and a second memory device (125,[0016-0017], fig. 1c) disposed within a projection of the second memory controller device (105 of 100c,[ 0024], fig.1c) in the vertical direction but fails to teach wherein the first non- volatile memory device and the first volatile memory device are entirely disposed within a projection of the first memory controller device in a vertical direction, wherein the second non-volatile memory device and the second volatile memory device are entirely disposed within a projection of the second memory controller device in the
vertical direction
However, Malladi et al discloses a non-volatile memory dies (226,[0041][0044], fig. 2) integrated with HBM dies(222,[0041][0044], fig. 2) on a controller die (220,[0041][0044][0047], fig. 2). It would have been obvious to one of ordinary skill in the art before the effective filing date to populate the memory controllers of Kirby et al with the with the non-volatile and volatile memory of Malladi et al such that wherein the first non- volatile memory device and the first volatile memory device are entirely disposed within a projection of the first memory controller device in a vertical direction, wherein the second non-volatile memory device and the second volatile memory device are entirely disposed within a projection of the second memory controller device in the
vertical direction results to increase memory capacity to scale storage performance.
Regarding claim 8, Kirby et al discloses wherein the logic device(160,[0024], fig. 1c) is electrically connected to the first memory controller device(105 of 100c,[ 0024], fig.1c), the interconnection device(185,[0030], fig. 1c) and the second memory controller device(105 of 100c,[ 0024], fig.1c) by hybrid bonding([0028] by way of 115).
Regarding claim 10, Kirby et al discloses wherein a gap between the logic device (160,[0024], fig. 1c) and the memory device (125,[0016-0017], fig. 1c) overlaps the first memory controller device(105 of 100c,[ 0024], fig.1c) in a vertical direction but fails to teach the memory device is the first non-volatile memory device.
However, Malladi et al discloses a non-volatile memory dies(226,[0041][0044], fig. 2) integrated with HBM dies(222,[0041][0044], fig. 2) on a controller die (220,[0041][0044][0047], fig. 2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kirby et al with the teachings of Malladi et al such that wherein a gap between the logic device and the first non-volatile memory device overlaps the first memory controller device in a vertical direction result to provide electrical connection between the processor die and controller.
Regarding claim 11, Kirby et al discloses wherein a gap between the logic device (160,[0024], fig. 1c) and the first volatile memory device(125,[0016-0017], fig. 1c) overlaps the first memory controller device(105 of 100c,[ 0024], fig.1c) in a vertical direction.
Regarding claim 12, Kirby et al discloses wherein a gap between the first memory controller device(105) and the interconnection device (185)overlaps the logic device(160) in a vertical direction fig. 1c.
Claim(s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kirby (US Pub no 2022/0157728 A1) in view of Malladi US Pub no. 2022/0300426 A1) as applied to claim 1 and further in view of Watanabe (US Pub no. 2018/0294249 A1).
Regarding claim 2, Kirby et al as modified by Malladi et al discloses all the claim limitations of claim 1 but fails to teach further comprising an encapsulant encapsulating the first memory controller device, the interconnection device and the second memory controller device.
Watanabe et al discloses a semiconductor device assembly comprising interconnection structure (107/107a, [0013], fig. 1/fig. 4)and intermediate dies (102c and 402c,[0017][0027],(semiconductor dies 102a-c, which includes the intermediate die, includes integrated circuit components such as memory control components ))that are encapsulated by a first mold material (104,[0016] [0028], fig. 1, fig. 4).It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Kirby et al & Malladi et al with the teachings of Watanabe et al to protect from physical damage that may occur in downstream manufacturing steps.
Regarding claim 3, Kirby et al in view of Watanabe et al discloses wherein a top surface and a bottom surface of the first memory controller device(102c,[0017][0027],(semiconductor dies 102a-c, which includes the intermediate die, includes integrated circuit components such as memory control components )) are substantially aligned with a top surface and a bottom surface of the encapsulant(104,[0016] [0028], fig. 1, fig. 4), respectively, wherein a top surface and a bottom surface of the second memory controller device(402c,[0017][0027],(semiconductor dies 102a-c, which includes the intermediate die, includes integrated circuit components such as memory control components )) are substantially aligned with the top surface and the bottom surface of the encapsulant(104,[0016] [0028], fig. 1, fig. 4), respectively(-Watanabe et al fig. 1/fig. 4).
Regarding claim 4, Kirby et al in view of Watanabe et al discloses wherein a top surface and a bottom surface of the interconnection device(107a/107, [0013], fig. 1/fig. 4)are substantially aligned with a top surface and a bottom surface of the encapsulant(104,[0016] [0028], fig. 1, fig. 4), respectively(-Watanabe et al).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kirby (US Pub no 2022/0157728 A1) in view of Malladi US Pub no. 2022/0300426 A1) as applied to claim 1 and further in view of Prasad (US Pub no. 2024/0088098 A1)
Regarding claim 9, Kirby et al as modified by Malladi et al discloses all the claim limitations of claim 1 but fails to teach wherein both of the first non-volatile memory device and the first volatile memory device are electrically connected to the first memory controller device by hybrid bonding.
However, Prasad et al discloses a hybrid memory architecture comprising hybrid bonding between memory dies (104,106,[0051]) and memory-interface/controller IC die (120,[0051]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Kirby et al & Malladi et al with the teachings of Prasad et al such that both of the first non-volatile memory device and the first volatile memory device are electrically connected to the first memory controller device by hybrid bonding results to provide communication with each other and/or transmit data signals, power and/or ground therethrough.
Related Prior Art
Su (US Pub no. 2020/0357766 A1) discloses An assembly structure, comprising: a substrate(1500,[0054]); an interconnection device(1200,[0052]) disposed over and electrically connected to the substrate(1500,[0054]); a first memory controller device(10) disposed over and electrically connected to the substrate(1500,[0054]); a first and second volatile memory (30,0050)on the first and second memory controller(10,[0050]) a device disposed over and electrically connected to the substrate(1500,[0054]), wherein the first memory controller device and the second memory controller device are disposed at different sides of the interconnection device(1200); a logic device(1300, processor chip,[0053]) disposed over and electrically connected to the interconnection device(1200,[0053] but fails to teach that the logic device is disposed over the first memory controller device and the second memory controller device; a first non-volatile memory device disposed over and electrically connected to the first memory controller device; a first volatile memory device disposed side by side with the first non-volatile memory device, and disposed over and electrically connected to the first memory controller device; a second non-volatile memory device disposed over and electrically connected to the second memory controller device; and a second volatile memory device disposed side by side with the second non-volatile memory device, and disposed over and electrically connected to the second memory controller device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
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/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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