Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-16 are pending in this action.
Information Disclosure Statement
The information disclosure statement (IDS) was not submitted for consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai (US 20200075117), in view of Ku (U2002/0,199,136)
As per claim 1:
As per claim 9:
Lai discloses:
A method for determining a memory testing coverage, comprising:
A method for determining a memory stability, comprising:
(Lai [0002] .. the test program of a memory device has designs, features, conditions and test patterns that can be adjusted manually and updated with different test phases to achieve the appropriate test coverage within a reasonable test time)
providing a plurality of testing programs, and testing
(Lai, Fig. 3, Performing the test program S308)
(Lai, Fig. 2 shows plurality of Test Program Version 1 to Version N, each version comprising a plurality of Test #1 toTest #9)
each of a plurality of memory dies by
(Lai [0016] .. the DUT 130 may be a semiconductor wafer that is divided into a plurality of dies, and each die may include an integrated circuit)
(Lai [0046] … the DUT 130 may be a semiconductor wafer, and the test items #1 to #4 are performed on the semiconductor wafer (e.g., including 7×7 dies), and each die may be an integrated circuit)
using one of the plurality of testing programs each time to
(Lai, Fig. 2 shows plurality of Test Program Version 1 to Version N, each version comprising a plurality of Test #1 to Test #9)
(Lai [0027] … Fig 2 version 1 of the test program (i.e., the first test iteration) includes a plurality of test items such as tests #1 to #89. … after the tests in the test program have been executed, the test results have to be manually inspected to select the test items that should be removed from or added to version 1 of the test program (i.e., subjective determination by manual inspection), such as removing test #3, test #5, and test #88, thereby generating version 2 of the test program … After the test program of each test iteration has been performed, manual inspection of the test results of the test program is required to select the test items to be added or removed…)
generate a failure bit information of each of the plurality of memory dies corresponding to each of the plurality of testing programs, wherein the plurality of testing programs are a plurality of independent programs;
(Lai, Fig. 3, Obtaining Test Results S310)
(Lai, [0036] FIGS. 4A-4D are diagrams of failure-bit maps of different test items ..., if the test program includes test items #1-#4, and the test results of the test items #1-#4 can be expressed by the failure-bit maps 410-440, as respectively illustrated in FIGS. 4A-4D)
acquiring the failure bit information of each of the plurality of memory dies tested with each of the plurality of testing programs as an input data;
(Lai, Fig. 3, Obtaining Test Results S310)
(Lai, [0036] FIGS. 4A-4D are diagrams of failure-bit maps of different test items ..., if the test program includes test items #1-#4, and the test results of the test items #1-#4 can be expressed by the failure-bit maps 410-440, as respectively illustrated in FIGS. 4A-4D)
acquiring a failure
(Lai, [0038]… each of the test items in the test program will be performed to generate a corresponding test result such as a failure-bit map. The test results may also include test yields or data logs, but the invention is not limited thereto)
(Lai, [0036] FIGS. 4A-4D are diagrams of failure-bit maps of different test items ..., if the test program includes test items #1-#4, and the test results of the test items #1-#4 can be expressed by the failure-bit maps 410-440, as respectively illustrated in FIGS. 4A-4D)
for each of the plurality of memory dies, acquiring a common failure bit address
(Lai, Figs 4A-4B shows a common failure location in column #4 and row #1)
(Lai, Figs 4 C shows a common failure location in row #1)
among the plurality of testing programs
(Lai, [0038] … FIG. 4A, the test item #1)
(Lai, [0038] … FIG. 4B, the test item #2)
(Lai, [0038] … FIG. 4C, the test item #3)
(Lai, [0038] … FIG. 4A, the test item #4)
or
a different failure bit
(Lai, Figs 4A-4B shows a different failure such as 411 and 421)
(Lai, Figs 4 C shows a different failure location in row #4)
based on the failure bit
(Lai, [0036] FIGS. 4A-4D are diagrams of failure-bit maps of different test items ..., if the test program includes test items #1-#4, and the test results of the test items #1-#4 can be expressed by the failure-bit maps 410-440, as respectively illustrated in FIGS. 4A-4D)
determining a testing coverage based on the common failure bit
(Lai, Figs 4A-4B shows a common failure location in column #4 and row #1)
(Lai, Figs 4 C shows a common failure location in row #1)
or
determining the testing coverage based on the different failure bit
(Lai, Figs 4A-4B shows a different failure such as 411 and 421)
(Lai, Figs 4 C shows a different failure location in row #4)
Lai discloses a method of receiving a failure-bit-map. However, Lai does not disclose “failure bit address”
Ku discloses:
failure bit address.
(Ku [0012] receiving a second test algorithm whose coverage differs from the initial test algorithm, and testing the chip in accordance with the second test algorithm; testing a memory array within the chip … generating a bit-map on the computer, from the failed address information, of failed bit locations within the memory array)…
(Ku, [0028] …In step 314, fail flag is set, a set of failed address information is loaded into the buffer 210. The failed address information includes the address which failed testing, the written data, the read-out data, and those bit locations within the address which failed. …. The buffer 210 temporarily holds the failed address information until copied by the communications module 116)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Ku’s method of outputting address information of failed bit location into the system in order to generate a failure bit map information based on failed address.
(Ku [0012] receiving a second test algorithm whose coverage differs from the initial test algorithm, and testing the chip in accordance with the second test algorithm; testing a memory array within the chip … generating a bit-map on the computer, from the failed address information, of failed bit locations within the memory array)…
(Ku, [0028] …In step 314, fail flag is set, a set of failed address information is loaded into the buffer 210. The failed address information includes the address which failed testing, the written data, the read-out data, and those bit locations within the address which failed. …. The buffer 210 temporarily holds the failed address information until copied by the communications module 116)
As per claim 2:
As per claim 10:
Lai-Ku further discloses:
successively recording each of the plurality of memory dies in a specific memory area when one of the plurality of testing programs performs a test;
(Lai, Fig. 2 shows a sequence of plurality of tests and the plurality of test programs performing a plurality of dies)
(Lai, [0036] FIGS. 4A shows failure-bit maps of different test items are recorded)
clearing the specific memory area after each of the plurality of testing programs completes testing; and
(Lai, [0036] FIGS. 4B shows a new failure-bit maps of different test items are recorded)
proceeding to a test performed by a next testing program of the plurality of testing programs.
(Lai, Fig. 2 shows a sequence of plurality of tests and the plurality of test programs performing a plurality of dies)
As per claim 3:
As per claim 11:
Lai-Ku further discloses:
wherein acquiring the common failure bit address further comprises: for each of the plurality of testing programs, decoding a failure bit address based on the failure bit information of each of the plurality of memory dies to obtain the failure bit
(Lai, [0036] FIGS. 4A-4D are diagrams of failure-bit maps of different test items ..., if the test program includes test items #1-#4, and the test results of the test items #1-#4 can be expressed by the failure-bit maps 410-440, as respectively illustrated in FIGS. 4A-4D)
Ku further discloses:
failure bit address.
(Ku [0012] receiving a second test algorithm whose coverage differs from the initial test algorithm, and testing the chip in accordance with the second test algorithm; testing a memory array within the chip … generating a bit-map on the computer, from the failed address information, of failed bit locations within the memory array)…
(Ku, [0028] …In step 314, fail flag is set, a set of failed address information is loaded into the buffer 210. The failed address information includes the address which failed testing, the written data, the read-out data, and those bit locations within the address which failed. …. The buffer 210 temporarily holds the failed address information until copied by the communications module 116)
In view of motivation previously stated, the claim is rejected.
As per claim 4:
As per claim 12:
Lai-Ku further discloses:
wherein when the common failure bit a
(Lai, [0036] FIGS. 4A-4D are diagrams of failure-bit maps of different test items ..., if the test program includes test items #1-#4, and the test results of the test items #1-#4 can be expressed by the failure-bit maps 410-440, as respectively illustrated in FIGS. 4A-4D)
(Lai [0002] .. the test program of a memory device has designs, features, conditions and test patterns that can be adjusted manually and updated with different test phases to achieve the appropriate test coverage within a reasonable test time)
Ku further discloses:
failure bit address.
(Ku [0012] receiving a second test algorithm whose coverage differs from the initial test algorithm, and testing the chip in accordance with the second test algorithm; testing a memory array within the chip … generating a bit-map on the computer, from the failed address information, of failed bit locations within the memory array)…
(Ku, [0028] …In step 314, fail flag is set, a set of failed address information is loaded into the buffer 210. The failed address information includes the address which failed testing, the written data, the read-out data, and those bit locations within the address which failed. …. The buffer 210 temporarily holds the failed address information until copied by the communications module 116)
In view of motivation previously stated, the claim is rejected.
As per claim 5:
As per claim 13:
Lai-Ku further discloses:
wherein when the different failure bit address among the plurality of testing programs is acquired, the failure bit testing programs is compared successively until all of the plurality of testing programs are compared so as to obtain the different failure bit address of each of the plurality of testing programs.
(Lai, Figs 4A-4B shows a common failure location in column #4 and row #1)
(Lai, Figs 4 C shows a common failure location in row #1)
(Lai, Figs 4A-4B shows a different failure such as 411 and 421)
(Lai, Figs 4 C shows a different failure location in row #4)
(Lai [0002] .. the test program of a memory device has designs, features, conditions and test patterns that can be adjusted manually and updated with different test phases to achieve the appropriate test coverage within a reasonable test time)
Ku further discloses:
failure bit address.
(Ku [0012] receiving a second test algorithm whose coverage differs from the initial test algorithm, and testing the chip in accordance with the second test algorithm; testing a memory array within the chip … generating a bit-map on the computer, from the failed address information, of failed bit locations within the memory array)…
(Ku, [0028] …In step 314, fail flag is set, a set of failed address information is loaded into the buffer 210. The failed address information includes the address which failed testing, the written data, the read-out data, and those bit locations within the address which failed. …. The buffer 210 temporarily holds the failed address information until copied by the communications module 116)
In view of motivation previously stated, the claim is rejected.
As per claim 6:
As per claim 14:
Lai-Ku further discloses:
wherein the different failure bit
(Lai, Figs 4A-4B shows a common failure location in column #4 and row #1)
(Lai, Figs 4 C shows a common failure location in row #1)
(Lai, Figs 4A-4B shows a different failure such as 411 and 421)
(Lai, Figs 4 C shows a different failure location in row #4)
(Lai [0002] .. the test program of a memory device has designs, features, conditions and test patterns that can be adjusted manually and updated with different test phases to achieve the appropriate test coverage within a reasonable test time)
Ku further discloses:
failure bit address.
(Ku [0012] receiving a second test algorithm whose coverage differs from the initial test algorithm, and testing the chip in accordance with the second test algorithm; testing a memory array within the chip … generating a bit-map on the computer, from the failed address information, of failed bit locations within the memory array)…
(Ku, [0028] …In step 314, fail flag is set, a set of failed address information is loaded into the buffer 210. The failed address information includes the address which failed testing, the written data, the read-out data, and those bit locations within the address which failed. …. The buffer 210 temporarily holds the failed address information until copied by the communications module 116)
In view of motivation previously stated, the claim is rejected.
As per claim 7:
As per claim 15:
Lai-Ku further discloses:
wherein the method is performed through an artificial intelligence calculation method.
(Lai, [0047] FIG. 5 is a diagram of the test-program neural network in accordance with an embodiment of the invention. As depicted in FIG. 5, the test-program neural network 500 may include a test-item layer 510, a failure-bit-map layer 520, an essential-test-item layer 530, a prioritized-weighting layer 540, and a next-test-item layer 550.
(Lai, [0004] he testing-control apparatus retrieves a test result of each of the first test items from the test equipment, and executes a test-program neural network to analyze the test result of each of the first test items to generate the test program for a next test iteration)
As per claim 8:
As per claim 16:
Lai-Ku further discloses:
wherein the plurality of testing programs comprise at least two testing programs.
(Lai, Fig. 2 shows a sequence of plurality of tests and the plurality of test programs performing a plurality of dies)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THIEN DANG NGUYEN whose telephone number is (571)272-9189. The examiner can normally be reached Monday-Friday 7 AM - 3:30 PM.
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/Thien Nguyen/Primary Examiner, Art Unit 2111