DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance: the pertinent prior art of record, and in light of such record as a whole under MPEP 1302.14 guidance, and further guidance under MPEP 2103, in brief and saliently: “the claim as a whole must be considered,” does not teach or suggest the combination of claim limitations making the whole of the claim(s) of the claimed invention, particularly as set forth in representative claim(s) 17 and 19.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim(s) 9 and 16 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein each of the phase-change memory cells comprises: a heater having a first end in electrical contact with a conductive region coupled to a selection transistor and a second end extending away from the conductive region; and a phase-change material feature including a data storage region electrically and thermally coupled to the second end of the heater, wherein the phase-change material feature is a continuous strip along a direction parallel to a major surface of a semiconductor body housing the selection transistor, and wherein a plurality of heaters is disposed at different locations along the continuous strip and separated by insulating regions; while in regard to claim 16, the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein each of the phase-change memory cells comprises: a heater having a first end in electrical contact with a conductive region coupled to a selection transistor and a second end extending away from the conductive region; and a phase-change material feature including a data storage region electrically and thermally coupled to the second end of the heater, wherein the phase-change memory device further comprises: a sealing layer of insulating material covering sidewalls of a stack comprising the heater and the data storage region, the sealing layer capping a top major surface of the data storage region.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. It is claimed, in part, “RESET programming voltage is approximately 3V.” Approximately 3V is open to any number of interpretations, which could lead to any number of outcomes. Is any voltage in the range from, i.e., 2-4 sufficiently approximate to 3V, how about 1V or 5V? The claim is found indefinite.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 10 and 14 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by US 20090129140 to Kawazoe et al. (“Kawazoe”).
As to claim 10, Kawazoe teaches A method for reading a phase-change memory device (As found in at least FIGS. 1-4, [0012], [0017]: operation of the memory cell array is described with the help of FIG. 3 which shows a read operation of a phase change memory (PCM)), the phase-change memory device comprising: a plurality of row lines (As found in at least FIG. 2: plurality or row lines WL#); a plurality of column lines (As found in at least FIG. 2: plurality of column lines BL#); a plurality of phase-change memory cells, each of the phase-change memory cells being coupled between the row line and one respective column line (As found in at least FIG. 2: plurality of PCM 10 coupled at cross-points of WL and BL), the method comprising: biasing one row line to which a phase-change memory cell to be read is connected, among the plurality of row lines, to a ground reference voltage (As found in at least [0010], [0012], FIG. 3: selected row line is biased at ground Vss); biasing the remaining row line of the plurality of row lines to a reading voltage (As found in at least FIG. 3: unselected row lines biased at reading volage V1); biasing the plurality of column lines to the reading voltage (As found in at least FIG. 3: plurality of column lines biased at V1); and acquiring, through a sense amplifier, a current flowing through the plurality of column lines to which the phase-change memory cells to be read is connected (As found in at least FIGS. 1-4: reading circuit 9 (amplifier) converts a reading current flowing in the bit line selected by the bit line decoder 2 among reading currents flowing in the bit line connected to the selected memory cell to a voltage, determines the state of memory data in the memory cell as a reading object connected to the selected bit line in the selected memory cells in one row, transfers its result to the control circuit 6d and outputs it to the data line 5).
As to claim 14, Kawazoe teaches coupling the sense amplifier to the plurality of column lines before the acquiring (As found in at least [0010] and at least FIG. 1: reading circuit (amplifier/determining circuit 9 connects to column (bit) lines before acquiring and determining state).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 20100067291 to Fuji (“Fuji”) in view of U.S. Patent/Publication No. 20200388753 to Karpov et al. (“Karpov”).
As to claim 1, Fuji teaches substantially the claimed invention, including, but not limited to: A method for programming a phase-change memory device (As found in at least [0003]).
While Fuji may not expressly including teachings of: “the phase-change memory device comprising: at least one row line; a plurality of column lines; a plurality of phase-change memory cells, each of the phase-change memory cells being coupled between the row line and one respective column line,” the teachings in Fuji, however, and in similitude to at least FIG. 2 of the drawings of the instant Application, include teachings of memory arrays [0021] that include phase change memory which in turn include column lines 801 and row lines Vg in at least FIGS. 1A-1B. Yet, further analysis follows below.
Fuji further teaches the method comprising: in a first operating condition associated with a first time interval, applying a RESET programming voltage to the plurality of phase-change memory cells, to program the plurality of phase-change memory cells to a first logic state (As found in at least FIG. 2, the Abstract, [0026]: reset programming that includes an amorphous state); and in a second operating condition associated with a second time interval that is subsequent to the first time interval, applying a SET programming voltage to selected phase-change memory cells among the plurality of phase-change memory cells, to program the selected phase-change memory cells to a second logic state (As found in at least FIG. 2, the Abstract, [0026]: set programming that includes an crystalline state), wherein the maximum voltage value of the RESET programming voltage is higher than that of the SET programming voltage (As found in at least FIG. 2: Reset voltage value higher than Set voltage value).
Moreover, Karpov, relevantly and complementarily teaches the phase-change memory device comprising: at least one row line; a plurality of column lines; a plurality of phase-change memory cells, each of the phase-change memory cells being coupled between the row line and one respective column line (As found in at least FIG. 1: phase change memory comprising column lines 105 and row lines 110, and phase change memory cells 120 coupled between them).
Fuji and Karpov are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: phase change memory having set and reset states.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Fuji as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Karpov also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: while Fuji may not expressly provide explicit illustrations of memory arrays comprising column and row lines, it is obvious, well-known and well-understood that this cross-point structure with a memory cell at the cross-point forms the basis of addressable memory devices; Karpov provides an example of such.
Therefore, it would have been obvious to combine Fuji with Karpov to make the above modification.
As to claim 6, Fuji teaches wherein the first time interval is shorter than the second time interval (As found in at least FIG. 2: first time interval for Reset is shorter than second time interval for Set).
As to claim 7, Fuji teaches wherein applying the RESET programming voltage comprises: activating a selection transistor coupled to a respective phase-change memory cell, wherein activating the selection transistor allows an electrical current to flow through the respective phase-change memory cell (As found in at least FIGS. 1A-1B and at least the Abstract: The first voltage is higher than the threshold voltage in the reset state, and can cause current to flow that corresponds to an amount of generated heat required for placing the element in the reset state).
Claim(s) 2-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 20100067291 to Fuji (“Fuji”) in view of U.S. Patent/Publication No. 20200388753 to Karpov et al. (“Karpov”), and further in view of US 10650889 to Berman (“Berman”).
As to claim 2, while Fuji as modified teaches substantially the claimed invention, including that programming Reset voltages are higher than programming Set voltages, wherein teachings in at least Fuji include the states associated with Reset and Set conditions: amorphous (high resistivity) and crystalline (low resistivity), and the necessary conditions to switch into these states, Fuji as modified may not expressly teach: wherein applying the RESET programming voltage comprises: biasing the at least one row line to a reference voltage; biasing the plurality of column lines to the RESET programming voltage; and biasing non-selected row lines to the RESET programming voltage.
Yet, Berman, relevantly and complementarily, obviates: wherein applying the RESET programming voltage comprises: biasing the at least one row line to a reference voltage (As found in at least FIG. 2C: row line WL3 set at a reference voltage); biasing the plurality of column lines to the RESET programming voltage (As found in at least FIG. 2C: MC13 and MC43 are cells undergoing Reset programming; their column lines BL1 and BL4 are set at a Vrst highest level, while BL2, BL3 and BL5, associated with non-selected memory cells are set at a Vrbl level lower than Vrst. The voltage difference between column lines and row lines for MC13 and MC43 is set so that said voltage difference is the highest to enable a programming Reset operation. The voltage difference between column lines and row lines for non-selected memory cells is set so that said voltage difference is not sufficient for a programming Reset operation: Vrbl=Vrwl=1V, therefore, the voltage difference between column lines and row lines for non-select memory cells is 0V); and biasing non-selected row lines to the RESET programming voltage (As found in at least FIG. 2C: non-select row lines are set at Vrwl; same analysis as above applies).
MPEP 2144.05(II) provides: “Routine Optimization.” “"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." As it applies to at least the teachings in Berman, it is not inventive to set non-select row lines to a RESET voltage, when in fact Vrwl as compared to Vrbl and Vrst provide workable voltage biasing. Any further beyond this is routine experimentation, not an inventive or novel discovery.
Fuji as modified and Berman are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: phase change memory having set and reset states.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Fuji as modified as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Berman also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: as set forth above.
Therefore, it would have been obvious to combine Fuji as modified with Berman to make the above modification.
As to claim 3, at least Berman teaches wherein the reference voltage is ground and the RESET programming voltage is approximately 3V (As found in at least FIG. 2C and related text, Vrst is 2V; 2V is “approximately” 3V).
As to claim 4, at least Berman teaches wherein applying the SET programming voltage comprises: biasing the at least one row line to a reference voltage; biasing column lines corresponding to the selected phase-change memory cells to the SET programming voltage; and biasing column lines corresponding to non-selected phase-change memory cells and non-selected row lines to an intermediate voltage (As found in at least FIG. 2B, related text, and in similitude to the analysis as set forth in the rejection to claim 2).
As to claim 5, see rejection to at least claim 4; moreover, Berman teaches in at least FIG. 2B and Column 9, lines 55-67, Column 10, lines 1-3: an intermediate voltage such as Vswl of 1V and a SET voltage Vset of 2V).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 20100067291 to Fuji (“Fuji”) in view of U.S. Patent/Publication No. 20200388753 to Karpov et al. (“Karpov”), and further in view of US 20130314984 to Scoville et al. (“Scoville”).
As to claim 8, while Fuji as modified teaches substantially the claimed invention, including a selection transistor coupled to a phase change memory as found in at least FIGS. 1A-1B, and while a Reset and/or programming voltage Vgst across the phase change memory cells is also found in such teachings, as well as a necessary gate voltage Vg at the gate of the selection transistor, the teachings may not expressly include: wherein activating the selection transistors comprises applying a voltage to gate terminals of the selection transistors, the voltage being higher than the RESET programming voltage by a threshold voltage of the selection transistors.
(As found in at least FIGS. 1A-1B, the selection transistor at its gate requires a voltage Vg to enable said transistor (conductive); Vg being sufficiently large to overcome the transistor’s threshold voltage; Vg does not need to overcome the cell programming voltage Vgst; also see at least [0016]).
Yet, relevantly and complementarily, Scoville teaches an “upside down” select transistor and PCM cell configuration. PCM 250 is coupled to select transistor 2240 at the source terminal of said 2240; the gate of 2240 is coupled to word line 230, and the drain terminal of 2240 is coupled to bit line 2220. Incidentally, at least FIG. 1 teaches an alternative configuration, where the select transistor couples the PCM cell at its drain terminal. The voltage at 2230, in the configuration of FIG. 2E, needs to overcome two voltages in series: the PCM programming voltage (Vgst in the teachings of Fuji) and the threshold voltage of select transistor 2240; that is the voltage at 2230 is required to be, if 2240 is to be conductive, higher than the RESET programming voltage, Vgst, by a threshold voltage of the selection transistors).
Fuji as modified and Scoville are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: phase change memory having set and reset states.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Fuji as modified as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Berman also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: Scoville teaches at least two transistor-PCM configurations: one in FIG. 2E that is labeled as “upside down,” and another in FIGS. 1 and 3; also see [0074]; Scoville teaches in at least [0025] that the configuration in FIGS. 1 and 3 “is somewhat preferable: the select transistor between ground and the PCM.
Therefore, it would have been obvious to combine Fuji as modified with Scoville to make the above modification.
Claim(s) 11 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by US 20090129140 to Kawazoe et al. (“Kawazoe”), and further in view of US 6646902 to Gilton et al. (“Gilton”).
As to claim 11, at least Gilton teaches wherein the reading voltage is selected to not change a programmed state of the phase-change memory cells (As found in at least claim 79).
Fuji as modified and Gilton are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: phase change memory having set and reset states.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Fuji as modified as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Gilton also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: Fuji in at least FIG. 4 teaches that a read voltage be lower than a program voltage, either for Reset or Set. While Fuji may not expressly teach that the read voltage is purposely made lower than the program voltage to prevent changing the programmed state, Gilton does so expressly. There cannot be a more obvious reason to set the read voltage lower than the program voltage so that the programmed state is not changed. The purpose is to detect the state, not to change it.
Therefore, it would have been obvious to combine Fuji as modified with Gilton to make the above modification.
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by US 20090129140 to Kawazoe et al. (“Kawazoe”), and further in view of US 20050122771 to Chen (“Chen”).
As to claim 12, at least Chen teaches wherein acquiring the current comprises: comparing the current flowing through the phase-change memory cell to be read with a reference current (As found in at least [0008]).
Fuji as modified and Chen are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: phase change memory having set and reset states.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Fuji as modified as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Chen also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: one way to determine whether a memory cell state comprises an expected value is to compare it with a reference value; whether the state is reflected by current or voltage is immaterial (after all, according to Ohm’s Law of V = I * R, where there is voltage V, there is current I).
Therefore, it would have been obvious to combine Fuji as modified with Chen to make the above modification.
As to claim 13, Chen teaches wherein the reference current is provided by a reference cell or a reference-current generator (As found in at least [0008]).
Claim(s) 15 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by US 20090129140 to Kawazoe et al. (“Kawazoe”), and further in view of US 2013031484 to Scoville et al. (“Scoville”).
As to claim 15, while Kawazoe teaches phase change memory cells in an array of PCM cells at cross-points of row and column lines, Kawazoe may not expressly teach wherein the phase-change memory device further comprises a plurality of selection transistors, each selection transistor coupled to a respective phase-change memory cell, the selection transistors being operable to address the phase-change memory cells during use of the phase-change memory device.
Yet, relevantly and complementarily, Scoville teaches wherein the phase-change memory device further comprises a plurality of selection transistors, each selection transistor coupled to a respective phase-change memory cell, the selection transistors being operable to address the phase-change memory cells during use of the phase-change memory device (As found in at least FIG. 1 and 2B, 2E: select transistors coupled to each PCM).
Kawazoe and Scoville are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: phase change memory having set and reset states.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Kawazoe as modified as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Scoville also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: Kawazoe teaches in at least [0023]: “a memory cell selecting circuit selecting the memory cell from the memory.” This is further elaborated in the teachings of Scoville in at least FIGS. 1 and 2E: a transistor coupled to a PCM. The advantage of this structure is that a single memory cell can be selected by means of addressing the selecting transistor.
Therefore, it would have been obvious to combine Kawazoe as modified with Scoville to make the above modification.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827