Prosecution Insights
Last updated: October 23, 2026
Application No. 18/885,727

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Non-Final OA §102§103§DOUBLEPATENT
Filed
Sep 15, 2024
Priority
Jul 05, 2019 — TW 108123743 +3 more
Examiner
VU, HUNG K
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
United Microelectronics Corp.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
899 granted / 1025 resolved
+19.7% vs TC avg
Moderate +9% lift
Without
With
+9.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
32 currently pending
Career history
1063
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
43.6%
+3.6% vs TC avg
§102
37.1%
-2.9% vs TC avg
§112
11.9%
-28.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1025 resolved cases

Office Action

§102 §103 §DOUBLEPATENT
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-9 of U.S. Patent No. 12,127,413. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations recited in claims of the instant application are encompassed by claims of U.S. Patent No. 12,127,413. Instant Application 18/885,727 Claim U.S. Patent No. 12,127,413 Claim 1 1, 5 2 2 3 3 4 4 5 1, 5 6 6 7 7 8 8 9 9 Claims 1-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-9 of U.S. Patent No. 11,004,897 in view of Yu et al. (US 2019/0165260). Regarding claim 1, Claim 1 of U.S. Patent No. 11,004,897 discloses a semiconductor device comprising: a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, wherein the first ULK dielectric layer comprises a first thickness; a passivation layer on the first ULK dielectric layer, wherein the passivation layer between the first MTJ and the second MTJ; and a second ULK dielectric layer on the passivation layer. Claim 1 of U.S. Patent No. 11,004,897 does not disclose the first thickness is greater than the second thickness. However, Yu et al. disclose a device having a passivation layer (630) having a second thickness (T2), and a first ULK (620) having a first thickness (T1) on a first MTJ (stack on the left, 530,535,540,545) and a second MTJ (stack on the right, 530,353,540,545) having a first thickness, and the first thickness is greater than the second thickness. See Figures 1-17, and [0057], [0087] of Yu et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form device of U.S. Patent No. 11,004,897 having the first thickness is greater than the second thickness, such as taught by Yu et al. in order to further prevent the coupling capacitance between the first MTJ and the second MTJ. Regarding claim 2, as similarly described above, Claim 1 of U.S. Patent No. 11,004,897 and Yu et al. disclose a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ. Regarding claim 3, as similarly described above, Claim 2 of U.S. Patent No. 11,004,897 and Yu et al. disclose a bottom surface of the passivation layer between the first MTJ and the second MTJ comprises a planar surface. Regarding claim 4, as similarly described above, Claim 3 of U.S. Patent No. 11,004,897 and Yu et al. disclose a sidewall of the passivation layer between the first MTJ and the second MTJ comprises a planar surface. Regarding claim 5, as similarly described above, Claim 1 of U.S. Patent No. 11,004,897 and Yu et al. disclose the passivation layer on top of the first MTJ comprises a third thickness. Regarding claim 6, as similarly described above, Claim 1 of U.S. Patent No. 11,004,897 and Yu et al. disclose further comprising a first top electrode on the first MTJ and a second top electrode on the second MTJ. Regarding claim 7, as similarly described above, Claim 5 of U.S. Patent No. 11,004,897 and Yu et al. disclose further comprising a first spacer around the first MTJ and a second spacer around the second MTJ. Regarding claim 8, as similarly described above, Claim 6 of U.S. Patent No. 11,004,897 and Yu et al. disclose a top surface of the first spacer is lower than a top surface of the first top electrode. Regarding claim 9, as similarly described above, Claim 7. of U.S. Patent No. 11,004,897 and Yu et al. disclose a top surface of the second spacer is lower than a top surface of the second top electrode. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2019/0165260). Yu et al. discloses, as shown in Figures 1-15, a semiconductor device comprising: a first magnetic tunneling junction (MTJ) (stack on the left, 530,535,540,545) and a second MTJ (stack on the right, 530,535,540,545) on a substrate (201, not shown, [0095]); a first ultra low-k (ULK) dielectric layer (620, (SiON, SiCN, or SiOCN, [0055],[0085]) on the first MTJ and the second MTJ, wherein the first ULK dielectric layer comprises a first thickness (T1); a passivation layer (630) on the first ULK dielectric layer, wherein the passivation layer between the first MTJ and the second MTJ comprises a second thickness (T2) and the first thickness (T1) is greater than the second thickness (T2) ([0057],[0087]); and a second ULK dielectric layer (640, [0063],[0087]) on the passivation layer. It is noted that the SiON, SiCN, or SiOCN layer can be read as the ultra low-k dielectric layer because the claim does not define how low is low. Regarding claim 2, Yu et al. disclose a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ. Regarding claim 3, Yu et al. disclose a bottom surface of the passivation layer between the first MTJ and the second MTJ comprises a planar surface. Regarding claim 4, Yu et al. disclose a sidewall of the passivation layer between the first MTJ and the second MTJ comprises a planar surface. Regarding claim 5, Yu et al. disclose the passivation layer on top of the first MTJ comprises a third thickness (Figures). Regarding claim 6, Yu et al. disclose further comprising a first top electrode (555) on the first MTJ and a second top electrode (555) on the second MTJ. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2019/0165260) in view of Chen et al. (PN 10,163,651). Regarding claim 7, Yu et al. discloses the claimed invention including the semiconductor device as explained in the above rejection. Yu et al. does not disclose a first spacer around the first MTJ and a second spacer around the second MTJ. However, Chen et al. discloses a semiconductor device comprising a first spacer (126) around a first MTJ (116) and a second spacer (126) around a second MTJ (116). Note Figures of Chen et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the device of Yu et al having a first spacer around the first MTJ and a second spacer around the second MTJ, such as taught by Chen et al. in order to protect the bottom electrode, the MTJ, and the top electrode from shortage. Regarding claim 8, Yu et al. and Chen disclose a top surface of the first spacer (126) is lower than a top surface of the first top electrode (118) [Figure 1]. Regarding claim 9, Yu et al. and Chen disclose a top surface of the second spacer (126) is lower than a top surface of the second top electrode (118) [Figure 1]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG K VU whose telephone number is (571)272-1666. The examiner can normally be reached Monday - Friday: 7am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JACOB CHOI can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HUNG K VU/ Primary Examiner, Art Unit 2897
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Prosecution Timeline

Sep 15, 2024
Application Filed
Oct 02, 2026
Non-Final Rejection mailed — §102, §103, §DOUBLEPATENT (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
97%
With Interview (+9.4%)
2y 6m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1025 resolved cases by this examiner. Grant probability derived from career allowance rate.

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