DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species A in the reply filed on 9/8/2026 is acknowledged.
Claims 5-6 and 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9/8/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 7, 8, 12, 14-16 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US 20180114834; herein “Cheng”).
Regarding claim 1, Cheng discloses in Fig. 10 and related text a structure comprising:
a field-effect transistor including a first source/drain region (e.g. 700A, see [0043]), a second source/drain region (e.g. 700B), a first nanosheet channel layer (e.g. 104C, see [0033]), a gate conductor layer (e.g. 1000, see [0048]), a first inner spacer (e.g. 500D, see [0039]), and a second inner spacer (e.g. portion of 108 remaining in Fig. 10, see [0035]), the first nanosheet channel layer extending laterally from the first source/drain region to the second source/drain region, the gate conductor layer including a first section positioned in a space above the first nanosheet channel layer, the first inner spacer adjoining the second inner spacer, and the first inner spacer and the second inner spacer positioned laterally between the first section of the gate conductor layer and the first source/drain region (see Fig. 10).
Regarding claim 2, Cheng discloses wherein the first inner spacer has a surface that is in direct contact with a surface of the second inner spacer (see Fig. 10).
Regarding claim 4, Cheng further discloses
a semiconductor substrate (e.g. 102),
wherein the first nanosheet channel layer (104C) is positioned between the first inner spacer (500D) and the semiconductor substrate, and the first inner spacer is positioned between the second inner spacer (remining portion of 108) and the first nanosheet channel layer.
Regarding claim 7, Cheng further discloses wherein the field-effect transistor includes a second nanosheet channel layer (e.g. 104B), and the gate conductor layer includes a second section in a space between the first nanosheet channel layer and the second nanosheet channel layer (see Fig. 10).
Regarding claim 8, Cheng further discloses wherein the field-effect transistor includes a gate dielectric layer (1002, see [0048]) between the first inner spacer and the gate conductor layer, and the gate dielectric layer comprises a high-k dielectric material.
Regarding claim 12, Cheng further discloses wherein the first nanosheet channel layer (100C) extends in a lateral direction, and the first inner spacer (500D) and the second inner spacer (108) are stacked in a vertical direction that is orthogonal to the lateral direction see Fig. 10).
Regarding claim 14, Cheng further discloses wherein the field-effect transistor includes a third inner spacer and a fourth inner spacer, and the third inner spacer adjoins the fourth inner spacer (e.g. 500D and 108 on opposite side).
Regarding claim 15, Cheng further discloses wherein the third inner spacer and the fourth inner spacer are laterally between the first section of the gate conductor layer and the second
Regarding claim 16, Cheng further discloses wherein the first section of the gate conductor layer is laterally between the second inner spacer and the fourth inner spacer (between 108 on left and 108 on right).
Regarding claim 18, Cheng further discloses wherein the first inner spacer is in direct contact with the second inner spacer, and the third inner spacer is in direct contact with the fourth inner spacer (see Fig. 10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3, 13, 14 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng as applied to claim 1 above, and in view of Rachmady et al. (US 20130341704; herein “Rachmady”).
Regarding claim 3, Cheng does not explicitly disclose wherein the surface of the first inner spacer has a first surface area, and the surface of second inner spacer has a second surface area that is greater than the first surface area.
In the same field of endeavor, Rachmady teaches in Fig. 1A and related text a semiconductor structure wherein the gate conductor layer (144, see [0019]) has multiple widths (see Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cheng by having the gate conductor layer has multiple widths, as shown by Rachmady, in order to achieve the desired gate width and drive current capacity (see abstract and [0023] at least).
The combined device therefore shows the surface of the first inner spacer (Cheng: 500D; Rachmady: uppermost 112) has a first surface area, and the surface of second inner spacer (Cheng: 108; Rachmady: 110B) has a second surface area that is greater than the first surface area.
Regarding claim 13, Cheng does not explicitly disclose wherein the gate conductor layer has multiple widths.
In the same field of endeavor, Rachmady teaches in Fig. 1A and related text a semiconductor structure wherein the gate conductor layer (144, see [0019]) has multiple widths (see Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cheng by having the gate conductor layer has multiple widths, as shown by Rachmady, in order to achieve the desired gate width and drive current capacity (see abstract and [0023] at least).
Regarding claim 14, the combined device shows wherein the field-effect transistor includes a third inner spacer and a fourth inner spacer, and the third inner spacer adjoins the fourth inner spacer (Cheng e.g. 500D and 108 on opposite side).
Regarding claim 17, the combined device shows wherein the first inner spacer the third inner spacer (Cheng: 500D; Rachmady: uppermost 112) have a first width, and the second inner spacer and the fourth inner spacer (Cheng: 108; Rachmady: 110B) have a second width greater than the first width (Rachmady: see Fig. 1A).
Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng as applied to claim 8 above, and in view of Zhou et al. (US 20250120108; herein “Zhou”).
Regarding claims 9-11, Cheng does not disclose
wherein the first inner spacer comprises silicon dioxide;
wherein the first inner spacer comprises a first dielectric material, and the second inner spacer comprises a second dielectric material different from the first dielectric material;
wherein the first inner spacer and the second inner spacer comprise a dielectric material.
In the same field of endeavor, Zhou teaches in Fig. 17 and related text a semiconductor structure comprising
wherein the first inner spacer (bottom “SiN” adjacent gate, see [0085]) comprises silicon dioxide;
wherein the first inner spacer (bottom “SiN” adjacent gate, see [0085]) comprises a first dielectric material, and the second inner spacer (top “SiN” adjacent gate, see [0085]) comprises a second dielectric material different from the first dielectric material (top can be silicon nitride oxide, see [0085]);
wherein the first inner spacer and the second inner spacer comprise a dielectric material (see [0085]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cheng by having the first inner spacer comprises silicon dioxide; the first inner spacer comprises a first dielectric material, and the second inner spacer comprises a second dielectric material different from the first dielectric material; the first inner spacer and the second inner spacer comprise a dielectric material, as taught by Zhou, in order to improve electrical isolation between the source/drain and the gate (see [0085]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896
