DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US 11862599) [Hereinafter Chen] further in view of Fujinaga et al (JPS62194638) [Hereinafter Fujinaga].
Regarding claim 1, Chen teaches A semiconductor device, comprising:
a first tier structure [wherein includes elements 20/20’, Fig. 10] comprising a plurality of conductive features [30/30T, para 19] of the first tier structure [para 18; wherein interconnect structure 27 comprises conductive features] positioned over a substrate [10, para 21], and a decoupling unit [28, Para 18] of the first tier structure positioned between the plurality of conductive features of the first tier structure;
a first set of solid alignment marks [50-DAM & 50-AM, para 25] comprising a first-tier- alignment mark [50-AM, para 25] positioned on the decoupling unit of the first tier structure [fig. 10];
a second tier structure [120/120’ para 28] positioned on the first tier structure [fig. 10] and comprising a plurality of conductive features [126/132/134, para 29] of the second tier structure over and deviated from the plurality of conductive features of the first tier structure [Fig. 10],
and a decoupling unit (128/133, Para 29) of the second tier structure positioned over the first tier structure [fig. 10], and positioned between the plurality of conductive features of the second tier structure [fig. 10];
and
a first set of spaced alignment marks [150-AM & 150-DAM, para 29] comprising a second-tier- alignment mark [150-AM, para 29] positioned on the decoupling unit of the second tier structure [fig. 10];
wherein the decoupling units of the first tier structure and the second tier structure comprise a low-k dielectric material [para 18 --wherein material 28 and 128 comprise similar materials, para 18/29] and respectively comprise a bottle-shaped cross-sectional profile (Fig. 10; it should be noted bottles come in various shapes to include rectangular cross-sectional profile).
wherein a width between two valleys of a sidewall of the decoupling unit of the first tier structure is greater than a width of a top surface of the first-tier-alignment mark of the first set of solid alignment marks [Wherein layer 28 is wider than that of the alignment marks in fig. 10].
Chen fails to explicitly disclose the first-tier- alignment mark comprising a fluorescence material;
a second-tier- alignment mark comprising a fluorescence material;
Fujinaga teaches in para 1 the use of alignment marks with fluorescence material to enable improved alignment with high accuracy
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have the alignment marks as taught by Chen comprising fluorescence material as taught by Fujinaga to enable improved alignment with high accuracy.
Claim(s) 2-3 & 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chen & Fujinaga as applied in clam 1 and further in view of Kuwana (JP 2021103225).
Regarding claim 2, Chen/Fujinaga teaches The semiconductor device of claim 1.
Chen/Fujinaga fails to explicitly disclose wherein the fluorescence material comprises azobenzene.
Kuwana teaches in the abstract an azo powder composition for alignment in semiconductor devices as optimal due to the material being hardly affected by static electricity, and a photo alignment material excellent in productivity and having alignment force and alignment sensitivity hardly affected by a temperature and humidity.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of fluorescence material for the alignment marks as taught by Fujinaga for high accuracy alignment with the azo powder composition as taught by Kuwana to increases reliability of the alignment marks.
Regarding claim 3, Chen/Fujinaga/Kawana teaches The semiconductor device of claim 2,
a first dielectric layer [buffer layer, para 21] positioned on the substrate;
a second dielectric layer [36, para 20] positioned on the first dielectric layer;
a middle dielectric layer [28/33, para 18/20] positioned on the second dielectric layer;
a third dielectric layer [40, para 22] positioned on the middle dielectric layer;
and a fourth dielectric layer [42, para 23] positioned on the third dielectric layer;
wherein the decoupling unit of the first tier structure is positioned in the middle dielectric layer and on the second dielectric layer [fig. 10];
Regarding claim 13, Chen/Fujinaga/Kawana teaches The semiconductor device of claim 3,
wherein the first-tier-alignment mark of the first set of solid alignment marks is positioned along the fourth dielectric layer and the third dielectric layer, extending to the middle dielectric layer, and on the decoupling unit of the first tier structure (Chen, fig. 10 –wherein according to the online merriam-webster dictionary “extending to” can be defined as
used as a function word to indicate movement or an action or condition suggestive of movement toward a place, person, or thing reached or
used as a function word to indicate direction]).
Claim 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, Fujinaga, & Kuwana as applied to claims 2-3 and further in view of Lo et al. (US 8653626).
Regarding claim 4, The semiconductor device of claim 3,
wherein the first dielectric layer and the third dielectric layer comprise the same material.
Chen specifically teaches the semiconductor device of claim 3, wherein the first layer may be formed of a Light-To-Heat-Conversion (LTHC) coating material (para 21) and the third dielectric layer comprises silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, or the like. (para 22)
Chen/Fujinaga/Kawana fails to explicitly disclose silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, or the like as LTHC coating materials.
However, Lo teaches (para 8) LTHC release coating 12 is, for example, an oxide, a nitride, an organic material, the like, or a combination thereof, such as silicon oxide, silicon nitride...
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention that silicon oxide & silicon nitride are LTHC coating materials and known in the art to function as dielectric materials that can be substituted as the material for the first layer. Thereby meeting the claim limitations of the first and third dielectric layers comprising the same material.
Regarding claim 5, Chen/Fujinaga/Kawana/Lo teaches The semiconductor device of claim 4,
wherein the second dielectric layer (Chen, fig. 10, 36) and the fourth dielectric layer (Chen, fig. 10, 42) comprise the same material. [Chen, para 20 & 23].
Regarding claim 6, Chen/Fujinaga/Kawana/Lo teaches The semiconductor device of claim 5,
wherein a sidewall of the first-tier-alignment mark of the first set of solid alignment marks is tapered. [Chen, fig. 10]
Claim 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Chen & Fujinaga as applied to claim 1 and further in view of Liu et al. (US 6277745).
Regarding claim 9, Chen/Fujinaga teaches The semiconductor device of claim 1.
Chen/Fujinaga fails to explicitly disclose wherein the plurality of conductive features of the first tier structure respectively comprises:
a bottom barrier layer positioned on the second dielectric layer;
a middle conductive layer positioned on the bottom barrier layer;
a top barrier layer positioned on the middle conductive layer;
and a spacer barrier positioned on sidewalls of the bottom barrier layer, the middle conductive layer, and the top barrier layer.
However, Liu teaches [fig. 1D] a method for the passivation of electrical interconnects comprising:
a bottom barrier layer [4, para 2] positioned on the second dielectric layer [wherein the plurality of conductors is on the second dielectric layer as taught by Chen];
a middle conductive layer [6, para 2] positioned on the bottom barrier layer;
a top barrier layer [8, para 2] positioned on the middle conductive layer;
and a spacer barrier [14, para 7] positioned on sidewalls of the bottom barrier layer, the middle conductive layer, and the top barrier layer.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to use the known technique taught by Liu for the plurality of conductive features in order to increase resistance to oxidation.
Regarding claim 10, Chen/Fujinaga/Liu teaches The semiconductor device of claim 9,
wherein the bottom barrier layer and the top barrier layer comprises the same material [Liu, para 2].
Regarding claim 11, The semiconductor device of claim 10,
wherein a thickness of the bottom barrier layer and a thickness of the top barrier layer are substantially the same.
Liu further teaches [para 3 & 4] wherein both top and bottom barrier layers is between 100 to 500 angstroms. It is noted that Liu further stated that thickness of the bottom barrier layer is usually thinner than that of the top barrier layer depending upon design rules and other considerations [Para 4].
At least based on Liu’s use of the term “usually” (where usually connotes “done most of the time but could be otherwise”), it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have the top and bottom layer carry a thickness that is substantially the same based on a finite number of identified, predictable potential solutions to the recognized need or problem (wherein, the thickness can only be the same or different).
Moreover, Liu statement that the thickness of the lower barrier layer is dependent on design rules (design choice), further suggests that the thickness of lower barrier layer can be adjusted as needed. Thus, it would have been obvious to a person having ordinary skills in the art to find the optimum thickness for the barrier layers, wherein in an instance the thicknesses are the same.
It should be noted that it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation” (MPEP 2144.05.II.A).
Furthermore, the depiction of barrier layers 4 and 8 in Liu’s invention suggests that the thicknesses of the layers are substantially the same. It is understood that figures are not considered to be an accurate representation of an invention unless there is a disclosure that the figures are drawn to scale. However, based on the depiction of Liu, a person having ordinary skills in the art will find it at least obvious to make the layers the same thickness based on the rationale of “Obvious to try” with a reasonable expectation of success (MPEP 2143.I.E).
Regarding claim 12, Chen/Fujinaga/Liu teaches The semiconductor device of claim 10,
wherein a thickness of the bottom barrier layer and a thickness of the top barrier layer are different [Liu, para 4, “usually, the lower barrier layer will be thinner…” Thereby meeting the claim limitation of the top and bottom barrier layer thicknesses to be different.].
Allowable Subject Matter
Claims 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7 Chen/Fujinaga teaches, The semiconductor device of claim 1.
The prior art of record fails to explicitly disclose wherein a width of a top surface of the first-tier-alignment mark of the first set of solid alignment marks is greater than a width of the first-tier-alignment mark of the first set of solid alignment marks at an interface between the middle dielectric layer and the third dielectric layer.
Thereby claim 7 contains allowable subject matter in light of the additional limitations recited therein.
Regarding claim 8, Chen/Fujinaga teaches The semiconductor device of claim 1.
The prior art of record fails to explicitly disclose wherein a width of a bottom surface of the first-tier-alignment mark of the first set of solid alignment marks is less than a width of the first-tier-alignment mark of the first set of solid alignment marks at an interface between the middle dielectric layer and the third dielectric layer.
Thereby claim 8 contains allowable subject matter in light of the additional limitations recited therein.
Conclusion
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/FELIX B ANDREWS/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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