Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
Applicant' s amendment dated 05/08/2026 in which claims 14-20 were cancelled, and claims 21-27 were added has been entered of record. Currently, claims 1-13 and 21-27 are pending in light of the amendment.
Election/Restrictions
Newly submitted claims 21-27 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
Claims 21-23. Claim 21 does not require the power circuit of claim1. Claim 1 does not require a first transistor of a first conductivity type and a second transistor of a second conductivity type of claim 21.
Claims 24-27. Claim 24 does not require receiving one of the first supply voltage or the second supply voltage based on whether a read condition is detected of claim 1. Claim 1 does not require outputting a detection signal based on a static noise margin of the modified memory cell of claim 24.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21-27 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 4, 7, 10, 11 and 13 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Nagle (U.S. Patent Application 9,330,751).
Claim 1. Nagle discloses a memory device, comprising: a power circuit comprising at least one first transistor and at least one second transistor coupled to a first line and a second line (Transistors 721/722 and 1121/1122 coupled to VDD/ VDD high supply lines and outputting wordline supply voltage VDD WL, Nagle Fig 7,11), wherein the first line is connected to a first supply voltage and the second line is connected to a second supply voltage; and a word line driver connected to a word line receiving one of the first supply voltage or the second supply voltage based on whether a read condition is detected (Wordline driver supply block that selects a wordline supply voltage based on read-assist control signals, Nagle Fig 6-7,11 Col 7 Lines 33-58).
Claim 3. The memory device of claim 1, wherein the at least one first transistor is connected parallel to the at least one second transistor, and wherein the at least one first transistor and the at least one second transistor are coupled between the first line and the second line (721 and 722 are connected in parallel in wordline driver supply circuit 720, Nagle Fig 7 Col 8 Lines 29-36).
Claim 4. The memory device of claim 1, wherein the second supply voltage is less than the first supply voltage (VDD_WL may fluctuate between low value VDD an high value VDD_High, Nagle Fig 4 Col 6 lines 45-52).
Claim 7. The memory device of claim 1, wherein the power circuit provides the first supply voltage to the word line driver in response to a detection of the read condition or the second supply voltage to the word line driver based on the read condition being undetected (Control signal A/B indicated whether to output wordline voltages for power gating, read-assist or write assist, supply circuit 620 outputs VDD_WL based on A/B, Nagle Fig 6-7 Col 7 Lines 41-58).
Claim 10. The memory device of claim 1, wherein the power circuit further comprises a resistor connected in series with the at least one second transistor (Line coupled to end of transistor 722 has resistance, thus acts as a resistor connected in series, Nagle Fig 7).
Claim 11. The memory device of claim 1, wherein the at least one second transistor comprises at least two transistors connected in series (transistors from 1112 and 1113 connected in series) and coupled between the first line and the second line (A/B), the at least two transistors connected in parallel to the at least one first transistor (721 and 722 in parallel, Nagle Fig 7).
Claim 13. The memory device of claim 1, further comprising: a plurality of memory cells connected to the word line, each of the plurality of memory cells powered by the first supply voltage (SRAM wordlines and a wordline driver supply block outputting VDD_WL to wordlines of the SRAM, Nagle Fig 5-65 Col 7 Lines 1-58).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 5, 6, 8 and 9 are rejected under 35 U.S.C. 103(a) as being unpatentable over Nagle (U.S. Patent Application 9,330,751) in view of Peng (U.S. Patent Application 7,636,268).
Claim 5. Nagle discloses the memory device of claim 1 but is silent with respect to wherein the read condition is detected based on a static noise margin being below a threshold.
Peng SRAM cells connected to a wordline, SNM (Static Noise Margin) detector controls a pull-down transistor to couple the wordline from GND, Peng Col 3 Lines 9-18 for the purpose of improving SRAM SNM operation in response to an SNM event.
Since Peng and Nagle are both from the same field of endeavor (SRAM wordline voltage assist control), the purpose disclosed by Peng would have been recognized in the pertinent art of Nagle.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the SNM detector taught by Peng to provide Nagle’s read assist control selecting the lower wordline supply voltage when an SNM even is detected the circuit for the purposes of improving SNM stability while avoiding unnecessary wordline lowering when there is no SNM issue (First output signal in response to an SNM even to couple WL to GND. Otherwise produced a second output signal to decouple the WL from GND, Claim 1).
Claim 6. Nagle discloses the memory device of claim 1, wherein the read condition is undetected based on a static noise margin being at or above a threshold (Peng teaches reference comparison does not detect an SNM even the WL is not pulled down thus the read condition is undetected based on a static noise margin being at or above a threshold, Peng Fig 6 Col 7 lines 31-46, same reason to combine as 5).
Claim 8. Nagle discloses the memory device of claim 1, further comprising: a detector circuit including a modified memory cell and configured to (configured to is functional language) output a signal indicating that a datum in the modified memory cell has flipped, the flipped datum indicating that the read condition is detected (Peng teaches an SNM detector having a reference cell, replica cell and comparator, where the replica cell produces a voltage and the reference cell produces and equalization voltage provided to the comparator, Peng Claim 1, same reason to combine as 5).
Claim 9. Nagle and Pend teach the memory device of claim 8, wherein source/drain (S/D) electrodes of each of the at least one first transistor and the at least one second transistor are connected to the first line and the second line (721/722 WL driver supply 720 receiving VDD/VDD High and control signals A/B), wherein a gate electrode of the at least one first transistor is connected to the detector circuit (Peng discloses and SNM detector output used to control wordline pulldown, Peng Abstract), and wherein a gate electrode of the at least one second transistor is connected to the first line.
Claims 2 and 12 are rejected under 35 U.S.C. 103(a) as being unpatentable over Nagle (U.S. Patent Application 9,330,751) in view of Houston (U.S. Patent Application 7,385,841).
Claim 2. Nagle teaches the memory device of claim 1, but is silent with respect to wherein the at least one first transistor is an n-type transistor or a p-type transistor, and wherein the at least one second transistor is the other type of transistor.
Houston teaches n-channel 240 and p channel 230 (Houston Fig 2) for the purpose of driving a WL in an SRAM using a voltage controlled driver (Houston, Col 4 lines 1-7).
Since Houston and Nagle are both from the same field of endeavor (SRAM wordline driver voltage), the purpose disclosed by Houston would have been recognized in the pertinent art of Nagle.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to connect Peng’s SNM detector output into the control path of Nagle supply transistor control for the purpose of driving a WL in an SRAM using a voltage controlled driver.
Claim 12. Nagle teaches the memory device of claim 1, but is silent with respect to wherein the word line driver comprises an inverter configured to (configured to is functional language) generate and output a word line signal via the word line according to the first supply voltage or the second supply voltage.
Houston teaches a WL driver formed by P and N 230/240 coupled in series to the power source, generating word out on the wordline (Houston Fig 2) for the purpose of driving a WL in an SRAM using a voltage controlled driver (Houston, Col 4 lines 1-7).
Since Houston and Nagle are both from the same field of endeavor (SRAM wordline driver voltage), the purpose disclosed by Houston would have been recognized in the pertinent art of Nagle.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to connect Peng’s SNM detector output into the control path of Nagle supply transistor control for the purpose of driving a WL in an SRAM using a voltage controlled driver.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571 )270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jason Lappas/
Primary Examiner, Art Unit 2827
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