DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,125,842 (hereinafter Patent’842). Although the claims at issue are not identical, they are not patentably distinct from each other because
Claim 1 of Patent’842 recites a structure comprising:
a silicon controlled rectifier (SCR) on a trap rich region of a semiconductor substrate (Col. 6, lines 1-2); and
at least one diode provided in a polysilicon material on a dielectric material and comprising a P+ region and an N+ region, separated by and directly contacting a p-type diffusion region (Col. 6, lines 3-14), wherein an N+ diffusion region of the SCR is provided in an n-well and connected to the P+ region of the at least one diode (Col. 6, lines 25-27), a second N+ diffusion region of the SCR is provided in a p-well and connected to the N+ region of the at least one diode and second P+ diffusion region of the SCR (Col. 6, lines 27-31), and the p-well and the n-well are over the trap rich region (Col. 6, lines 31-21).
Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 10 of Patent’842. Although the claims at issue are not identical, they are not patentably distinct from each other because
Claim 10 of Patent’842 recites a structure comprising at least one diode provided in a polysilicon material directly on a dielectric material and vertically integrated with a silicon controlled rectifier (SCR) (Col. 6, lines 66-67; Col. 7, lines 1-3), the at least one diode comprising a gate structure including a P+ region and an N+ region, separated by and contacting a p-type diffusion region (Col. 7, lines 3-6; lines 18-20), the N+ diffusion region of the SCR being connected to a P+ region of the at least one diode, a second N+ diffusion region of the SCR being connected to the N+ region of the at least one diode and a second P+ diffusion region of the SCR (Col. 7, lines 12-16), and an underlying semiconductor substrate comprises a p-well under the dielectric material and an n-well adjacent to the p-well (Col. 7, lines 7-9).
Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 of Patent’842. Although the claims at issue are not identical, they are not patentably distinct from each other because
Claim 17 of Patent’842 recites a method comprising:
forming a silicon controlled rectifier (SCR) on a trap rich region of a semiconductor substrate (Col. 8, lines 5-6); and
forming at least one diode provided in a polysilicon material on a dielectric material and comprising a P+ region and an N+ region, separated by and directly contacting a p-type diffusion region (Col. 8, lines 7-18), wherein an N+ diffusion region of the SCR is provided in an n-well and connected to the P+ region of the at least one diode, a second N+ diffusion region of the SCR is provided in a p-well and connected to the N+ region of the at least one diode and second P+ diffusion region of the SCR (Col. 8, lines 30-36), and the p-well and the n-well are over the trap rich region (Col. 8, lines 36-37).
Claim Objections
Claims 16-18 are objected to because of the following informalities:
Claim 16 recites “wherein the at least one diode comprises a trigger element comprises multiple diodes in series, each of which comprise..” which should be replaced with
“wherein the at least one diode comprises a trigger element comprising multiple diodes in series, each of which comprises..”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 10-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention
Claim 3 (claim 10) recites limitation “the P+ diffusion region”. There is insufficient antecedent basis for this limitation in the claim because it is unclear whether “the P+ diffusion region” relates back to “a p-type diffusion region” (lines 5-6 of claim 1), “second P+ diffusion region” (line 9 of claim 1), or to set forth an additional P+ diffusion region.
Claim 11 recites limitation “the N+ diffusion region” (line 4) that lacks antecedent basis in the claim 11.
Claim 11 recites limitation “a P+ region” twice (in line 3 and line 5). It is unclear whether the second recited “a P+ region” (line 5) is intended to relate back to previously recited “a P+ region” (line 3) or to set forth an additional P+ region.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-6, 8-9, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 7,728,349 to Boselli in view of Schneider et al. (US 2009/0185316, cited in IDS of 09/16/2024, hereinafter Schneider), Mitra et al. (US 2020/0411504, cited in IDS of 09/16/2024, hereinafter Mitra), and Chang (US 2004/0065923, cited in IDS of 09/16/2024).
With respect to claims 1-2 and 8, Boselli discloses a structure (e.g., silicon control rectifier with diode trigger element) (Boselli, Fig. 7A, Col. 1, lines 6-9; Col. 2, lines 15-47; Col. 11, lines 1-55) comprising:
a silicon controlled rectifier (e.g., SCR 700) (Boselli, Fig. 7A, Col. 11, lines 1-55) on a semiconductor substrate (702) (Boselli, Fig. 7A, Col. 4, lines 1-3; Col. 11, lines 21); and
at least one diode (e.g., a trigger element 722 including a series of diodes formed by PN junctions) (Boselli, Fig. 7A, Col. 11, lines 9-11, lines 38-40; lines 50-55) provided on the semiconductor substrate (702) and comprising a P region and an N region, wherein an N diffusion region (710) (Boselli, Fig. 7A, Col. 11, lines 29-33) of the SCR is provided in an n-well (704) and connected to the P region of the at least one diode (722), a second N diffusion region (714) (Boselli, Fig. 7A, Col. 11, lines 33-38) of the SCR is provided in a p-well (706) and connected to the N region of the at least one diode (722) and second P diffusion region (716) of the SCR, and the p-well (706) and the n-well (704) are over the semiconductor substrate (702) (as claimed in claim 1);
wherein the at least one diode (722) (Boselli, Fig. 7A, Col. 11, lines 16-20) is vertically above the SCR.
Further, Boselli does not specifically disclose (1) a trap rich region of a semiconductor substrate; and the p-well and the n-well are over the trap rich region (as claimed in claim 1); wherein the trap rich region is defective silicon material (as claimed in claim 8); (2) at least one diode provided in a polysilicon material on a dielectric material and comprising a P+ region and an N+ region, separated by and directly contacting a p-type diffusion region; an N+ diffusion region of the SCR, a second N+ diffusion region of the SCR, and second P+ diffusion region of the SCR (as claimed in claim 1); wherein the at least one diode is integrated with the SCR (as claimed in claim 2).
Regarding (1), Schneider teaches forming electrostatic discharge (ESD) protection device (Schneider, Figs. 3-4, ¶0009, ¶0018, ¶0029-¶0031, ¶0039, ¶0043, ¶0050) comprising a semiconductor substrate (e.g., silicon) including a trap rich region with increased defect density and concentration of deep traps to provide fast avalanche response in the device, wherein the trap rich region (e.g., 306) (Schneider, Figs. 3-4, ¶0031, ¶0039, ¶0043) is formed by implanting impurity atoms including argon and nitrogen in a portion of the N-type buried region (303) under the N-type well (304) and the P-type well (305) of the semiconductor device (e.g., a diode 300 in Fig. 3 or bipolar transistor 400 including a diode, as in Fig. 4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Boselli by forming a defect region having increased defect density and concentration of deep traps in a semiconductor substrate and under the p-well and the n-well as taught by Schneider, wherein the defect region is formed as a trap rich region by implanting impurity atoms including argon to have the structure comprising: a trap rich region of a semiconductor substrate; and the p-well and the n-well are over the trap rich region (as claimed in claim 1); wherein the trap rich region is defective silicon material (as claimed in claim 8), in order to provide fast avalanche response in the electrostatic discharge (ESD) protection device (Schneider, ¶0009, ¶0018, ¶0029-¶0031).
Regarding (2), Mitra teaches forming a diode triggered silicon control rectifiers (Mitra, Figs. 1-4, ¶0004-¶0006, ¶0012-¶0027) comprising at least one diode (e.g., a diode string 25a/25b) (Mitra, Figs. 2-3, ¶0015, ¶0022, ¶0026) provided in a polysilicon material on a gate dielectric material (e.g., P+ regions 24a and N+ regions 24b including doped poly P-doped 62a and N-doped poly 62b material are formed on a gate dielectric material) (Mitra, Figs. 2-3, ¶0026) and comprising a P+ region (62a) and an N+ region (62b) over the semiconductor substrate (12a), wherein the SCR (110) (Mitra, Figs. 2-3, ¶0023, ¶0024) comprises an N+ diffusion region (54b) of the SCR, a second N+ diffusion region (54b’) of the SCR, and second P+ diffusion region (54a’) of the SCR.
Further, Chang teaches forming a silicon controlled rectifier (SCR) including PN junctions (e.g., 203/204 and 204/205) (Chang, Figs. 6-7, ¶0029, ¶0032) on the gate dielectric material (218) (Chang, Figs. 6-7, ¶0028, ¶0033) and comprising a third diffusion (e.g., buffer region 208) of the first dopant type (e.g., p-type) separating the first diffusion region (203) from the second diffusion region (204), to suppress junction leakage current (Chang, Figs. 6-7, ¶0032).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the structure of Boselli by forming at least one trigger diode on the dielectric layer over the semiconductor substrate as taught by Mitra, wherein the at least one diode comprises PN junctions including a diffusion region having lower doped concentration and separating the N-type diffusion region and the P-type diffusion region as taught by Chang to have the structure comprising: at least one diode provided in a polysilicon material on a dielectric material and comprising a P+ region and an N+ region, separated by and directly contacting a p-type diffusion region; an N+ diffusion region of the SCR, a second N+ diffusion region of the SCR, and second P+ diffusion region of the SCR (as claimed in claim 1); wherein the at least one diode is integrated with the SCR (as claimed in claim 2), in order to provide low leakage ESD protection device including the diode triggered SCR; and to provide improved structure which is insensitive to substrate noise, and having suppressed junction leakage current (Mitra, ¶0012, ¶0013, ¶0019, ¶0026; Chang, ¶0026, ¶0032, ¶0033).
Regarding claim 4, Boselli in view of Schneider, Mitra, and Chang discloses the structure of claim 1. Further, Boselli discloses the structure, wherein the at least one diode (722) comprises a diode string (e.g., series of diodes) (Boselli, Fig. 7A, Col. 11, lines 9-20; lines 50-52) comprising multiple diodes, but does not specifically disclose that the at least one diode comprises multiple diodes in polysilicon material.
However, Mitra teaches forming a diode triggered silicon control rectifiers (Mitra, Figs. 1-4, ¶0004-¶0006, ¶0012-¶0027) including the at least one diode (e.g., a diode string 25a/25b) (Mitra, Figs. 2-3, ¶0015, ¶0022, ¶0026) that comprises multiple diodes in a polysilicon material (e.g., P+ regions 24a and N+ regions 24b including doped poly P-doped 62a and N-doped poly 62b material are formed on a gate dielectric material) (Mitra, Figs. 2-3, ¶0026).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the structure of Boselli/Schneider/Mitra/Chang by forming at least one trigger diode in a polysilicon material as taught by Mitra to have the structure, wherein the at least one diode comprises multiple diodes in polysilicon material, in order to provide low leakage ESD protection device including the diode triggered SCR (Mitra, ¶0012, ¶0013, ¶0019, ¶0026).
Regarding claim 5, Boselli in view of Schneider, Mitra, and Chang discloses the structure of claim 4. Further, Boselli discloses the structure, wherein the multiple diodes are in series (Boselli, Fig. 7A, Col. 11, lines 9-20; lines 50-52).
Regarding claim 6, Boselli in view of Schneider, Mitra, and Chang discloses the structure of claim 4. Further, Boselli does not specifically disclose that the multiple diodes are connected by a silicide material.
However, Mitra teaches forming a diode triggered silicon control rectifiers (Mitra, Figs. 1-4, ¶0004-¶0006, ¶0012-¶0027) including the at least one diode (e.g., a diode string 25a/25b) (Mitra, Figs. 2-3, ¶0015, ¶0022, ¶0026) that comprises multiple diodes electrically connected by a silicide (e.g., silicide contacts are formed over the P+ and N+ regions 24a/24b of the diodes 25a and 25b) (Mitra, Figs. 2-3, ¶0021).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the structure of Boselli/Schneider/Mitra/Chang by forming at least one trigger diode comprising multiple diodes as taught by Mitra to have the structure, wherein the multiple diodes are connected by a silicide material, in order to provide low leakage ESD protection device including the diode triggered SCR (Mitra, ¶0012, ¶0013, ¶0019, ¶0026).
Regarding claim 9, Boselli in view of Schneider, Mitra, and Chang discloses the structure of claim 4. Further, Boselli discloses the structure, wherein the SCR comprises a PNPN (Boselli, Fig. 7A, Col. 11, lines 16-20; Col. 8, lines 24-30).
With respect to claim 20, Boselli discloses a method (e.g., forming a silicon control rectifier with diode trigger element) (Boselli, Fig. 7A, Col. 1, lines 6-9; Col. 2, lines 15-47; Col. 11, lines 1-55) comprising:
forming a silicon controlled rectifier (e.g., SCR 700) (Boselli, Fig. 7A, Col. 11, lines 1-55) on a semiconductor substrate (702) (Boselli, Fig. 7A, Col. 4, lines 1-3; Col. 11, lines 21); and
forming at least one diode (e.g., a trigger element 722 including a series of diodes formed by PN junctions) (Boselli, Fig. 7A, Col. 11, lines 9-11, lines 38-40; lines 50-55) provided on the semiconductor substrate (702) and comprising a P region and an N region, wherein an N diffusion region (710) (Boselli, Fig. 7A, Col. 11, lines 29-33) of the SCR is provided in an n-well (704) and connected to the P region of the at least one diode (722), a second N diffusion region (714) (Boselli, Fig. 7A, Col. 11, lines 33-38) of the SCR is provided in a p-well (706) and connected to the N region of the at least one diode (722) and second P diffusion region (716) of the SCR, and the p-well (706) and the n-well (704) are over the semiconductor substrate (702).
Further, Boselli does not specifically disclose (1) a trap rich region of a semiconductor substrate; and the p-well and the n-well are over the trap rich region; (2) forming at least one diode provided in a polysilicon material on a dielectric material and comprising a P+ region and an N+ region, separated by and directly contacting a p-type diffusion region; an N+ diffusion region of the SCR, a second N+ diffusion region of the SCR, and second P+ diffusion region of the SCR.
Regarding (1), Schneider teaches forming electrostatic discharge (ESD) protection device (Schneider, Figs. 3-4, ¶0009, ¶0018, ¶0029-¶0031, ¶0039, ¶0043, ¶0050) comprising a semiconductor substrate (e.g., silicon) including a trap rich region with increased defect density and concentration of deep traps to provide fast avalanche response in the device, wherein the trap rich region (e.g., 306) (Schneider, Figs. 3-4, ¶0031, ¶0039, ¶0043) is formed by implanting impurity atoms including argon and nitrogen in a portion of the N-type buried region (303) under the N-type well (304) and the P-type well (305) of the semiconductor device (e.g., a diode 300 in Fig. 3 or bipolar transistor 400 including a diode, as in Fig. 4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Boselli by forming a defect region having increased defect density and concentration of deep traps in a semiconductor substrate and under the n-type well and the p-type well as taught by Schneider, wherein the defect region is formed as a trap rich region by implanting impurity atoms including argon to have the method comprising: a trap rich region of a semiconductor substrate; and the p-well and the n-well are over the trap rich region, in order to provide fast avalanche response in the electrostatic discharge (ESD) protection device (Schneider, ¶0009, ¶0018, ¶0029-¶0031).
Regarding (2), Mitra teaches forming a diode triggered silicon control rectifiers (Mitra, Figs. 1-4, ¶0004-¶0006, ¶0012-¶0027) comprising at least one diode (e.g., a diode string 25a/25b) (Mitra, Figs. 2-3, ¶0015, ¶0022, ¶0026) provided in a polysilicon material on a gate dielectric material (e.g., P+ regions 24a and N+ regions 24b including doped poly P-doped 62a and N-doped poly 62b material are formed on a gate dielectric material) (Mitra, Figs. 2-3, ¶0026) and comprising a P+ region (62a) and an N+ region (62b) over the semiconductor substrate (12a), wherein the SCR (110) (Mitra, Figs. 2-3, ¶0023, ¶0024) comprises an N+ diffusion region (54b) of the SCR, a second N+ diffusion region (54b’) of the SCR, and second P+ diffusion region (54a’) of the SCR.
Further, Chang teaches forming a silicon controlled rectifier (SCR) including PN junctions (e.g., 203/204 and 204/205) (Chang, Figs. 6-7, ¶0029, ¶0032) on the gate dielectric material (218) (Chang, Figs. 6-7, ¶0028, ¶0033) and comprising a third diffusion (e.g., buffer region 208) of the first dopant type (e.g., p-type) separating the first diffusion region (203) from the second diffusion region (204), to suppress junction leakage current (Chang, Figs. 6-7, ¶0032).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the method of Boselli by forming at least one trigger diode on the dielectric layer over the semiconductor substrate as taught by Mitra, wherein the at least one diode comprises PN junctions including a diffusion region having lower doped concentration and separating the N-type diffusion region and the P-type diffusion region as taught by Chang to have the method comprising: forming at least one diode provided in a polysilicon material on a dielectric material and comprising a P+ region and an N+ region, separated by and directly contacting a p-type diffusion region; an N+ diffusion region of the SCR, a second N+ diffusion region of the SCR, and second P+ diffusion region of the SCR, in order to provide low leakage ESD protection device including the diode triggered SCR; and to provide improved structure which is insensitive to substrate noise, and having suppressed junction leakage current (Mitra, ¶0012, ¶0013, ¶0019, ¶0026; Chang, ¶0026, ¶0032, ¶0033).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 7,728,349 to Boselli in view of Schneider (US 2009/0185316), Mitra (US 2020/0411504), and Chang (US 2004/0065923) as applied to claim 1, and further in view of Okumura (US 2013/0175549, cited in IDS of 09/16/2024).
Regarding claim 3, Boselli in view of Schneider, Mitra, and Chang discloses the structure of claim 1. Further, Boselli does not specifically disclose the structure, wherein (1) the dielectric material is a gate dielectric material of a gate structure, the P+ diffusion region connects to an anode and the N+ diffusion region connects to the P+ region provided on a first side of the gate structure, and the second N+ diffusion region connects to the N+ region and the second P+ diffusion region connects to a cathode provided on a second side of the gate structure; (2) a gate dielectric material which directly contacts the p-well above the trap rich region.
Regarding (1), Mitra teaches forming a diode triggered silicon control rectifiers (Mitra, Figs. 1-4, ¶0004-¶0006, ¶0012-¶0027) including the at least one diode (e.g., a diode string 25a/25b) (Mitra, Figs. 2-3, ¶0015, ¶0022, ¶0026) isolated from the semiconductor substrate (12a) by the gate dielectric material of a gate structure (e.g., P-doped poly 62a and N-doped poly 62b are formed on a gate dielectric material) (Mitra, Figs. 2-3, ¶0026), the P+ diffusion region (54a) (Mitra, Figs. 2-3, ¶0024) connects to an anode and the N+ diffusion region connects (54b) to the P+ region (62a) provided on a first side of the gate structure.
Further, Mitra teaches forming P+ region (18a) and N+ region (18b) on a second side of the gate structure such that the P+ diffusion region (18a), N-well 52 and p-type substrate form PNP transistor 27 (Mitra, Figs. 3-4, ¶0019) which is connected to the cathode, which acts as a very low leakage diode, wherein the N+ diffusion region (54b’) connected to the cathode is connected to the N+ region (62b) through the P+ diffusion region (18a) formed on a second side of the gate structure.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the structure of Boselli/Schneider/Mitra/Chang by forming at least one trigger diode on the gate dielectric layer of the gate structure over the semiconductor substrate, and arranging multiple P+ regions and N+ regions on both sides of the gate structure as taught by Mitra to have the structure, wherein the dielectric material is a gate dielectric material of a gate structure, the P+ diffusion region connects to an anode and the N+ diffusion region connects to the P+ region provided on a first side of the gate structure, and the second N+ diffusion region connects to the N+ region and the second P+ diffusion region connects to a cathode provided on a second side of the gate structure, in order to provide low leakage ESD protection device including the diode triggered SCR (Mitra, ¶0012, ¶0013, ¶0019, ¶0026).
Regarding (2), Okumura teaches forming a semiconductor device (Okumura, Fig. 2, ¶0006, ¶0056-¶0057, ¶0068-¶0069, ¶0084-¶0085) comprising a gate protection diode, wherein the gate dielectric material (19) is directly contacting the p-well (13) of an underlying substrate (5/8), to protect the threshold value of the adjacent device from varying, and to prevent from the gate insulating layer from being destroyed.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the structure of Boselli/Schneider/Mitra/Chang by arranging a diode structure comprising multiple PN junctions on the gate insulating layer directly contacting the p-well of the substrate as taught by Okumura to have the structure, wherein the gate dielectric material is directly contacting the p-well of an underlying substrate above the trap rich region, in order to provide a diode structure to protect the threshold value of the adjacent device from varying, and to prevent from the gate insulating layer from being destroyed (Okumura, ¶0006, ¶0068-¶0069, ¶0084-¶0085).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 7,728,349 to Boselli in view of Schneider (US 2009/0185316), Mitra (US 2020/0411504), and Chang (US 2004/0065923) as applied to claim 4, and further in view of Li et al. (US Patent No. 10,008,491, cited in IDS of 09/16/2024, hereinafter Li).
Regarding claim 7, Boselli in view of Schneider, Mitra, and Chang discloses the structure of claim 4. Further, Boselli does not specifically disclose that the multiple diodes are oriented perpendicular to a width of the SCR. However, Li teaches forming a compact structure (Li, Figs. 1, 2A, Col 2, lines 15-28; Col. Col. 3, lines 60-67; Col. 4, lines 1-67; Col. 5, lines 1-15) comprising a PNPN silicon controlled rectifier on the bulk substrate comprising n-type well 14 and p-type well 16, and alternating patterns of the P+ regions (120a’ and 120c’) and N+ region (120b’) to from a diode, wherein the alternating patterns are oriented perpendicular to a width of the silicon controlled rectifier.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the method of Boselli/Schneider/Mitra/Chang by forming multiple diodes oriented as alternating patterns of the P+ regions and N+ region of Li, wherein the alternating patterns are oriented perpendicular to the orientation of the silicon controlled rectifier to have the structure, wherein the multiple diodes are oriented perpendicular to a width of the SCR, in order to provide a compact structure comprising improved ESD SCR device having reduced total device area (Li, Col. 2, lines 15-28; Col. 4, lines 29-32).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 7,728,349 to Boselli in view of Schneider (US 2009/0185316), Mitra (US 2020/0411504), and Chang (US 2004/0065923) as applied to claim 1, and further in view of Deivasigamani et al. (US Patent No. 10,475,885, cited in IDS of 09/16/2024, hereinafter Deivasigamani).
Regarding claim 10, Boselli in view of Schneider, Mitra, and Chang discloses the structure of claim 1. Further, Boselli does not specifically disclose the structure, (1) wherein the at least one diode is isolated from the semiconductor substrate by the dielectric material, the P+ diffusion region of the SCR is connected to an anode and the second P+ diffusion region of the SCR is connected to a cathode, and (2) the p-well and the n-well directly contact the trap rich region.
Regarding (1), Mitra teaches forming a diode triggered silicon control rectifiers (Mitra, Figs. 1-4, ¶0004-¶0006, ¶0012-¶0027) including the at least one diode (e.g., a diode string 25a/25b) (Mitra, Figs. 2-3, ¶0015, ¶0022, ¶0026) isolated from the semiconductor substrate (12a) by the gate dielectric material, the P+ diffusion region (54a) (Mitra, Fig. 3, ¶0023-¶0025) of the SCR (110) is connected to an anode and the second P+ diffusion region (54a’) of the SCR (110) is connected to a cathode.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the structure of Boselli/Schneider/Mitra/Chang by forming at least one trigger diode comprising multiple diodes over the substrate and connected to the SCR as taught by Mitra to have the structure, wherein at least one diode is isolated from the semiconductor substrate by the dielectric material, the P+ diffusion region of the SCR is connected to an anode and the second P+ diffusion region of the SCR is connected to a cathode, in order to provide low leakage ESD protection device including the diode triggered SCR (Mitra, ¶0012, ¶0013, ¶0019, ¶0026).
Regarding (2), Deivasigamani teaches forming a structure (Deivasigamani, Fig. 2, Col. 1, lines 44-65; Col. 4, lines 37-67; Col. 5, lines 1-37; Col. 6, lines 42-56; Col. 7, lines 1-6; Col. 8, lines 12-16) comprising multiple PN junctions, wherein the P+ diffusion region (e.g., 131a/131b) in the p-well (e.g.,119a/119b) is connected to an anode (e.g.,145a/145b), and the N+ diffusion region (133) in the n-well (e.g.,121) is connected to a cathode (e.g.,147), and the p-well (e.g.,119a/119b) and the n-well (e.g.,121) directly contact the buried implant region (e.g.,109a-109c), to prevent leakage current problem.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the method of Boselli/Schneider/Mitra/Chang by forming the p-well and the n-well over the buried implant region as taught by Deivasigamani, wherein the buried implant region includes the trap rich region of Boselli/Schneider to have the structure, wherein the p-well and the n-well directly contact the trap rich region, in order to provide improved structure comprising multiple PN junctions having prevented leakage current problem (Deivasigamani, Col. 1, lines 44-65; Col. 5, lines 22-37; Col. 8, lines 21-36).
Claims 11 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0411504 to Mitra in view of Chang (US 2004/0065923).
With respect to claims 11, Mitra discloses a structure (e.g., diode triggered silicon control rectifiers) (Mitra, Figs. 3-4, ¶0004-¶0006, ¶0012-¶0027) comprising at least one diode (e.g., a diode string 25a/25b) (Mitra, Figs. 3-4, ¶0015, ¶0022, ¶0026) in a polysilicon material (e.g., P+ -doped poly gate material 62a and N+ -doped poly gate material 62b formed by conventional deposition process of poly gate material are interpreted as a polysilicon material) directly on a dielectric material (e.g., P+ -doped poly gate material 62a and N+ -doped poly gate material 62b are formed on a gate dielectric material) (Mitra, Figs. 3-4, ¶0026) and vertically integrated with the silicon controlled rectifier (SCR) (e.g., 110, SCR) (Mitra, Fig. 3, ¶0022-¶0026), the N+ diffusion region (54b) of the SCR (110) being connected to a P+ region (62a) of the at least one diode, a second N+ diffusion region (54b’) of the SCR being connected (e.g., through the p-type substrate, N-well 20, and P+ region 18a) to the N+ region (62b) of the at least one diode and a second P+ diffusion region (54a’) of the SCR (110), and an underlying semiconductor substrate comprises a p-well (50) (Mitra, Fig. 3, ¶0023) under the dielectric material and an n-well (52) adjacent to the p-well (50).
Further, Mitra does not specifically disclose a P+ region and an N+ region, separated by and contacting a p-type diffusion region.
However, Chang teaches the structure, wherein multiple diode structures (e.g., PN junction 203/208/204 and 204/209/205) are provided in a polysilicon material (Chang, Figs. 6-7, ¶0026) comprising a P region (203, 205) and an N region (204), separated by a p-type diffusion region (208 or 209) (Chang, Figs. 6-7, ¶0030), and that a p-type diffusion region (208 or 209) has a doped concentration lower than other p-type doped regions (e.g., 201, 203, 205), wherein the P regions (203, 205), the N region (204), and the p-type diffusion region (208 or 209) are directly contacting the gate dielectric material (218) (Chang, Figs. 6-7, ¶0028, ¶0033).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the structure of Mitra by forming multiple diodes comprising PN junctions including a diffusion region having lower doped concentration between the P-type diffusion region and the N-type diffusion region as taught by Chang to have the structure comprising the at least one diode comprising a P+ region and an N+ region, separated by and contacting a p-type diffusion region, in order to provide improved structure which is insensitive to substrate noise, and having suppressed junction leakage current (Chang, ¶0026, ¶0032, ¶0033).
Regarding claim 13, Mitra in view of Chang discloses the structure of claim 11. Further, Mitra discloses the structure, wherein the SCR comprises an anode (54a) (Mitra, Fig. 3, ¶0024, ¶0025) over the n-well (52) and a cathode (54b’) over the p-well (50).
Regarding claim 14, Mitra in view of Chang discloses the structure of claim 13. Further, Mitra discloses the structure, wherein a P+ diffusion region (54a) (Mitra, Fig. 3, ¶0023-¶0025) of the SCR (110) connects to the anode, the N+ diffusion region (54b) connects to the P+ region (62a) of the at least one diode, the second N+ diffusion region (54b’) connects (e.g., through the p-type substrate, N-well 20, and P+ region 18a) to the N+ region (62b) of the at least one diode, and a second P+ diffusion region (54a’) connects to the cathode and the N+ diffusion region (54b’).
Regarding claim 15, Mitra in view of Chang discloses the structure of claim 11. Further, Mitra discloses the structure, wherein the least one diode (e.g., a diode string 25a/25b) (Mitra, Figs. 2-3, ¶0015, ¶0022, ¶0026) comprises a gate structure comprising the P+ region (62a) and the N+ region (62b), but does not specifically disclose that the P+ region and the N+ region are separated by the p-type diffusion region.
However, Chang teaches the structure, wherein multiple diode structures (e.g., PN junction 203/208/204 and 204/209/205) are provided in a polysilicon material (Chang, Figs. 6-7, ¶0026) comprising a P region (203, 205) and an N region (204), separated by a p-type diffusion region (208 or 209) (Chang, Figs. 6-7, ¶0030), and that a p-type diffusion region (208 or 209) has a doped concentration lower than other p-type doped regions (e.g., 201, 203, 205).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the structure of Mitra/Chang by forming multiple diodes comprising PN junctions including a diffusion region having lower doped concentration between the P-type diffusion region and the N-type diffusion region as taught by Chang to have the structure, wherein the at least one diode comprising the P+ region and the N+ region separated by the p-type diffusion region, in order to provide improved structure which is insensitive to substrate noise, and having suppressed junction leakage current (Chang, ¶0026, ¶0032, ¶0033).
Claims 12, 16-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0411504 to Mitra in view of Chang (US 2004/0065923) as applied to claim 11, and further in view of Schneider (US 2009/0185316).
Regarding claims 12 and 19, Mitra in view of Chang discloses the structure of claim 11. Further, Mitra does not specifically disclose the structure, wherein the SCR is on a trap rich region of a silicon substrate (as claimed in claim 12); wherein the trap rich region is defective silicon material (as claimed in claim 19).
However, Schneider teaches forming electrostatic discharge (ESD) protection device (Schneider, Figs. 3-4, ¶0009, ¶0018, ¶0029-¶0031, ¶0039, ¶0043, ¶0050) comprising a silicon substrate (Schneider, Figs. 3-4, ¶0039) including a trap rich region with increased defect density and concentration of deep traps to provide fast avalanche response in the device, wherein the trap rich region (e.g., 306) (Schneider, Figs. 3-4, ¶0031, ¶0039, ¶0043) is formed by implanting impurity atoms including argon and nitrogen in a portion of the N-type buried region (303) under the N-type well (304) and the P-type well (305) of the semiconductor device (e.g., a diode 300 in Fig. 3 or bipolar npn transistor 400 including a diode, as in Fig. 4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Mitra/Chang by forming a defect region having increased defect density and concentration of deep traps in a semiconductor substrate as taught by Schneider, wherein the defect region is formed as a trap rich region by implanting impurity atoms including argon in a portion of the semiconductor substrate of Mitra under the N-type well and the P-type well to have the structure, wherein the SCR is on a trap rich region of a silicon substrate (as claimed in claim 12); wherein the trap rich region is defective silicon material (as claimed in claim 19), in order to provide fast avalanche response in the electrostatic discharge (ESD) protection device (Schneider, ¶0009, ¶0018, ¶0029-¶0031).
Regarding claim 16, Mitra in view of Chang and Schneider discloses the structure of claim 12. Further, Mitra discloses the structure, wherein the at least one diode comprises a trigger element comprising multiple diodes (e.g., a diode string 25a/25b) (Mitra, Figs. 2-3, ¶0015, ¶0022, ¶0026) in series (Mitra, Figs. 2-4, ¶0006, ¶0020, ¶0027), but does not specifically disclose that each of which comprises the P+ region and the N+ region are separated by the p-type diffusion region.
However, Chang teaches the structure, wherein multiple diode structures (e.g., PN junction 203/208/204 and 204/209/205) are provided in a polysilicon material (Chang, Figs. 6-7, ¶0026) comprising a P region (203, 205) and an N region (204), separated by a p-type diffusion region (208 or 209) (Chang, Figs. 6-7, ¶0030), and that a p-type diffusion region (208 or 209) has a doped concentration lower than other p-type doped regions (e.g., 201, 203, 205).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the structure of Mitra/Chang/Schneider by forming multiple diodes comprising PN junctions including a diffusion region having lower doped concentration between the P-type diffusion region and the N-type diffusion region as taught by Chang to have the structure, comprising multiple diodes, each of which comprises the P+ region and the N+ region separated by the p-type diffusion region, in order to provide improved structure which is insensitive to substrate noise, and having suppressed junction leakage current (Chang, ¶0026, ¶0032, ¶0033).
Regarding claim 17, Mitra in view of Chang and Schneider discloses the structure of claim 16. Further, Mitra discloses the structure, wherein the multiple diodes are electrically connected by a silicide (e.g., silicide contacts are formed over the P+ and N+ regions 24a/24b of the diodes 25a and 25b) (Mitra, Figs. 2-3, ¶0021).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0411504 to Mitra in view of Chang (US 2004/0065923) and Schneider (US 2009/0185316) as applied to claim 16, and further in view of Li (US Patent No. 10,008,491).
Regarding claim 18, Mitra in view of Chang and Schneider discloses the structure of claim 16. Further, Mitra does not specifically disclose that the multiple diodes are oriented perpendicular to a width of the silicon controlled rectifier. However, Li teaches forming a compact structure (Li, Figs. 1, 2A, Col 2, lines 15-28; Col. Col. 3, lines 60-67; Col. 4, lines 1-67; Col. 5, lines 1-15) comprising a PNPN silicon controlled rectifier on the bulk substrate comprising n-type well 14 and p-type well 16, and alternating patterns of the P+ regions (120a’ and 120c’) and N+ region (120b’) to from a diode, wherein the alternating patterns are oriented perpendicular to a width of the silicon controlled rectifier.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the method of Mitra/Chang/Schneider by forming multiple diodes oriented as alternating patterns of the P+ regions and N+ region of Li, wherein the alternating patterns are oriented perpendicular to the orientation of the silicon controlled rectifier to have the structure, wherein the multiple diodes are oriented perpendicular to a width of the silicon controlled rectifier, in order to provide a compact structure comprising improved ESD SCR device having reduced total device area (Li, Col. 2, lines 15-28; Col. 4, lines 29-32).
Conclusion
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/NATALIA A GONDARENKO/ Primary Examiner, Art Unit 2891
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