DETAILED ACTION
This Office Action is in response to Applicant’s application 18/886,950 filed on September 16, 2024 in which claims 1 to 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on September 16, 2024 have been reviewed and accepted by the Examiner.
Information Disclosure Statement
The Information Disclosure Statements (IDS), filed on September 16, 2024, March 23, 2026 and August 31, 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Priority
Receipt is acknowledged of paper submitted under 35 U.S.C. 119(a)-(d) or under 35 U.S.C. 120, 121, 365(c), or 386(c) which has been placed of record in the file.
Notation
References to patents will be in the form of [C:L] where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of [xxxx].
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 5 which recites the limitation "the first contact" and “the second contact” in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 7, the same analysis applies.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. U.S. 12,101,976 (‘976). Although the claims at issue are not identical, they are not patentably distinct from each other as discussed below.
Table 1 – Comparison of Pending Claim to ‘976 Claims
Pending Claim
‘976 Claim
1. An electronic device comprising a display panel including a plurality of pixels, each of the plurality of pixels including:
a light-emitting diode including an anode; a power line which receives a power voltage;
an initialization voltage line which receives an initialization voltage;
a signal line which receives a signal;
a bias voltage line which receives a bias voltage; a first transistor electrically connected between the power line and the anode of the light-emitting diode; and
a second transistor electrically connected between a data line and a first reference node,
wherein in a plan view, the signal line does not overlap the power line.
1. An electronic device comprising a display panel including a plurality of pixels, each of the plurality of pixels including:
a light-emitting diode including an anode; a power line which receives a power voltage;
an initialization voltage line which receives an initialization voltage;
an initialization signal line which receives an initialization signal;
a bias voltage line which receives a bias voltage; a first transistor electrically connected between the power line and the anode of the light-emitting diode;
a second transistor electrically connected between a data line and a first reference node;
a third transistor including a first gate in contact with the initialization signal line through a first contact and electrically connected between the initialization voltage line and the anode; and
a fourth transistor including a second gate in contact with the initialization signal line through a second contact different from the first contact and electrically connected between the power line and the bias voltage line,
wherein in a plan view, the initialization signal line does not overlap the power line.
2. The electronic device of claim 1, wherein the signal line is extended in a first direction, and the power line is extended in a second direction crossing the first direction.
2. The electronic device of claim 1, wherein the initialization signal line is extended in a first direction, and the power line is extended in a second direction crossing the first direction.
3. The electronic device of claim 2, wherein the initialization voltage line is extended in the first direction.
3. The electronic device of claim 2, wherein the initialization voltage line is extended in the first direction.
4. The electronic device of claim 3, wherein a width of the initialization voltage line along the second direction is larger than a width of the bias voltage line along the second direction.
4. The electronic device of claim 3, wherein a width of the initialization voltage line along the second direction is larger than a width of the bias voltage line along the second direction.
5. The electronic device of claim 2, wherein in the plan view, the first contact and the second contact are spaced apart from each other in the first direction.
5. The electronic device of claim 2, wherein in the plan view, the first contact and the second contact are spaced apart from each other in the first direction.
6. The electronic device of claim 1, wherein a width of the signal line along a direction perpendicular to a main extension direction of the signal line is larger than a width of the bias voltage line along the direction perpendicular to the main extension direction of the signal line.
6. The electronic device of claim 1, wherein a width of the initialization signal line along a direction perpendicular to a main extension direction of the initialization signal line is larger than a width of the bias voltage line along the direction perpendicular to the main extension direction of the initialization signal line.
7. The electronic device of claim 1, further comprising: a third transistor including a first gate in contact with the signal line through a first contact and electrically connected between the initialization voltage line and the anode; and
a fourth transistor including a second gate in contact with the signal line through a second contact different from the first contact and electrically connected between the power line and the bias voltage line, and
wherein the first gate and the second gate are integrated, and the second gate is extended in a main extension direction of the signal line from the first gate.
From claim 1
a third transistor including a first gate in contact with the initialization signal line through a first contact and electrically connected between the initialization voltage line and the anode; and
a fourth transistor including a second gate in contact with the initialization signal line through a second contact different from the first contact and electrically connected between the power line and the bias voltage line,
7. The electronic device of claim 1, wherein
the first gate and the second gate are integrated, and the second gate is extended in a main extension direction of the initialization signal line from the first gate.
8. The electronic device of claim 7, wherein the power line comprises a first power line portion overlapping the first gate and the second gate in the plan view and a second power line portion non-overlapping the first gate and the second gate, and a first width of the first power line portion along a direction perpendicular to a main extension direction of the power line is smaller than a second width of the second power line portion along the direction perpendicular to the main extension direction of the power line.
8. The electronic device of claim 1, wherein the power line comprises a first power line portion overlapping the first gate and the second gate in the plan view and a second power line portion non-overlapping the first gate and the second gate, and a first width of the first power line portion along a direction perpendicular to a main extension direction of the power line is smaller than a second width of the second power line portion along the direction perpendicular to the main extension direction of the power line.
9. The electronic device of claim 7, wherein in the plan view, at least one of the first gate and the second gate overlaps the power line.
9. The electronic device of claim 1, wherein in the plan view, at least one of the first gate and the second gate overlaps the power line.
10. The electronic device of claim 7, wherein the signal line comprises
a first signal line and a second signal line
spaced apart in a main extension direction of the signal line from the first signal line, wherein:
the first signal line contacts the first gate through the first contact; and the second signal line contacts the second gate through the second contact.
10. The electronic device of claim 1, wherein the initialization signal line comprises
a first initialization signal line and a second initialization signal line
spaced apart in a main extension direction of the initialization signal line from the first initialization signal line, wherein:
the first initialization signal line contacts the first gate through the first contact; and the second initialization signal line contacts the second gate through the second contact.
11. The electronic device of claim 10, wherein the first signal line and the second signal line are electrically connected through the first gate and the second gate.
11. The electronic device of claim 10, wherein the first initialization signal line and the second initialization signal line are electrically connected through the first gate and the second gate.
12. The electronic device of claim 7, wherein the third transistor and the fourth transistor are turned on in response to the signal.
12. The electronic device of claim 1, wherein the third transistor and the fourth transistor are turned on in response to the initialization signal.
13. The electronic device of claim 12, further comprising: a fifth transistor electrically connected between the first transistor and a second reference node; a sixth transistor electrically connected between the initialization voltage line and the second reference node; a seventh transistor electrically connected between a reference power line to which a reference voltage is applied and the first reference node; an eighth transistor electrically connected between the first transistor and the anode; and a ninth transistor electrically connected between the power line and the fourth transistor.
13. The electronic device of claim 1, further comprising: a fifth transistor electrically connected between the first transistor and a second reference node; a sixth transistor electrically connected between the initialization voltage line and the second reference node; a seventh transistor electrically connected between a reference power line to which a reference voltage is applied and the first reference node; an eighth transistor electrically connected between the first transistor and the anode; and a ninth transistor electrically connected between the power line and the fourth transistor.
14. An electronic device comprising a display panel including a plurality of pixels, each of the plurality of pixels including:
a light-emitting diode including an anode;
a power line which receives a power voltage;
a signal line which receives a signal and includes:
a first line portion overlapping the power line in a plan view; and
a second line portion non-overlapping the power line in the plan view;
an initialization voltage line which receives an initialization voltage;
a bias voltage line which receives a bias voltage;
a first transistor electrically connected between the power line and the anode of the light-emitting diode; and
a second transistor electrically connected between a data line and a first reference node, wherein:
a first width of the first line portion along a direction perpendicular to a main extension direction of the signal line is smaller than a second width of the second line portion along the direction perpendicular to the main extension direction of the signal line.
14. An electronic device comprising a display panel including a plurality of pixels, each of the plurality of pixels including:
a light-emitting diode including an anode;
a power line which receives a power voltage;
an initialization signal line which receives an initialization signal and includes:
a first line portion overlapping the power line in a plan view; and
a second line portion non-overlapping the power line in the plan view;
an initialization voltage line which receives an initialization voltage;
a bias voltage line which receives a bias voltage;
a first transistor electrically connected between the power line and the anode of the light-emitting diode;
a second transistor electrically connected between a data line and a first reference node;
a third transistor including a first gate in contact with the initialization signal line through a first contact and electrically connected between the initialization voltage line and the anode; and
a fourth transistor including a second gate in contact with the initialization signal line through a second contact different from the first contact and electrically connected between the power line and the bias voltage line, wherein:
a first width of the first line portion along a direction perpendicular to a main extension direction of the initialization signal line is smaller than a second width of the second line portion along the direction perpendicular to the main extension direction of the initialization signal line.
15. The electronic device of claim 14, wherein a width of the bias voltage line along the direction perpendicular to the main extension direction of the signal line is larger than the first width but smaller than the second width.
15. The electronic device of claim 14, wherein a width of the bias voltage line along the direction perpendicular to the main extension direction of the initialization signal line is larger than the first width but smaller than the second width.
16. The electronic device of claim 14, wherein the signal line is extended in a first direction, and the power line is extended in a second direction crossing the first direction.
16. The electronic device of claim 14, wherein the initialization signal line is extended in a first direction, and the power line is extended in a second direction crossing the first direction.
17. The electronic device of claim 14, wherein the power line comprises a first power line portion overlapping the signal line and a second power line portion non-overlapping the signal line, and a first width of the first power line portion along a direction perpendicular to a main extension direction of the power line is smaller than a second width of the second power line portion along the direction perpendicular to the main extension direction of the power line.
17. The electronic device of claim 14, wherein the power line comprises a first power line portion overlapping the initialization signal line and a second power line portion non-overlapping the initialization signal line, and a first width of the first power line portion along a direction perpendicular to a main extension direction of the power line is smaller than a second width of the second power line portion along the direction perpendicular to the main extension direction of the power line.
18. The electronic device of claim 14, further comprising:
a third transistor including a first gate in contact with the signal line through a first contact and electrically connected between the initialization voltage line and the anode; and
a fourth transistor including a second gate in contact with the signal line through a second contact different from the first contact and electrically connected between the power line and the bias voltage line, and
wherein the first gate and the second gate are integrated, and the second gate is extended in the main extension direction of the signal line from the first gate.
From claim 14
a third transistor including a first gate in contact with the initialization signal line through a first contact and electrically connected between the initialization voltage line and the anode; and
a fourth transistor including a second gate in contact with the initialization signal line through a second contact different from the first contact and electrically connected between the power line and the bias voltage line, wherein:
18. The electronic device of claim 14,
wherein the first gate and the second gate are integrated, and the second gate is extended in the main extension direction of the initialization signal line from the first gate.
19. The electronic device of claim 18, wherein in the plan view, at least one of the first gate and the second gate overlaps the power line.
19. The electronic device of claim 14, wherein in the plan view, at least one of the first gate and the second gate overlaps the power line.
20. The electronic device of claim 18, wherein the third transistor and the fourth transistor are turned on in response to the signal.
20. The electronic device of claim 14, wherein the third transistor and the fourth transistor are turned on in response to the initialization signal.
Regarding claim 1 and referring to Table 1, Examiner notes the pending claim 1 recites a signal line while claim 1 of the ’976 recites an initialization signal line. Examiner takes the position that a signal line has the same structure as an initialization signal line and therefore the structure of pending claim 1 is disclosed in claim 1 of the ‘976 patent.
Regarding claims 2-13, Examiner notes this subject matter is described in claims 1-13 of the ‘’976 patent.
Regarding claim 14 and referring to Table 1, Examiner notes the pending claim 14 recites a signal line while claim 14 of the ’976 recites an initialization signal line. Examiner takes the position that a signal line has the same structure as an initialization signal line and therefore the structure of pending claim 14 is disclosed in claim 14 of the ‘976 patent.
Regarding claims 15-20 Examiner notes this subject matter is disclosed in claims 14-20 of the ‘976 patent.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST.
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/J.E. Schoenholtz/Primary Examiner, Art Unit 2893
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