DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim 20220102584 in view of Lin et al. 20190279972
Regarding Claim 1, in Figs. 6 and 7, Kim discloses a display device comprising: a substrate SUB; a pixel circuit layer PCL disposed on the substrate; and a display element layer DPL disposed on the pixel circuit layer, wherein the display element layer comprises: a first bank BNK including a first opening OP1; a first light emitting element disposed in the first opening, and including a first bonding electrode CNE1 and a second bonding electrode CNE2, the first bonding electrode being electrically connected to an electrode of a first transistor disposed in the pixel circuit layer, Kim fails to disclose the limitations, a second bank disposed on the first bank, and including a second opening at least partially overlapping the first opening in a vertical direction; and a second light emitting element disposed in the second opening, and including a third bonding electrode and a fourth bonding electrode, the third bonding electrode being electrically connected to the second bonding electrode. However, Lin et al. discloses a display device where in Figs 6 and 7 and paragraphs 0063 and 0067 the required limitation of , a second bank disposed on the first bank, and including a second opening at least partially overlapping the first opening in a vertical direction; and a second light emitting element disposed in the second opening, and including a third bonding electrode and a fourth bonding electrode, the third bonding electrode being electrically connected to the second bonding electrode (see elements R2 and R3) is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required, a second bank disposed on the first bank, and including a second opening at least partially overlapping the first opening in a vertical direction; and a second light emitting element disposed in the second opening, and including a third bonding electrode and a fourth bonding electrode, the third bonding electrode being electrically connected to the second bonding electrode, in Kim as taught by Lin et al. in order to have compact display device.
Regarding Claim 2, in paragraphs 0112, 0113, 0140 and 0141 and Fig. 7 of Kim, wherein the display element layer further comprises: a first anode electrode disposed under the first bank, and electrically connected to the electrode of the first transistor; and a first reflective electrode disposed on the first anode electrode and the first bank, and connecting the first bonding electrode and the first anode electrode.
Regarding Claim 3, in paragraphs 0112, 0113, 0140 and 0141 and Fig. 7 of Kim, wherein the display element layer further comprises: a first cathode electrode disposed under the first bank; and a second reflective electrode disposed on the first cathode electrode and the first bank, and connecting the second bonding electrode and the first cathode electrode.
Regarding Claim 4, in paragraphs 0112, 0113, 0140 and 0141 and Fig. 7 of Kim, wherein the display element layer further comprises a second anode electrode connecting the second reflective electrode and the third bonding electrode.
Regarding Claim 5, in paragraphs 0112, 0113, 0140 and 0141 and Fig. 7 of Kim, wherein the display element layer further comprises: a common electrode connected in common to a plurality of sub-pixel circuits; and a second cathode electrode electrically connecting the fourth bonding electrode and the common electrode.
Regarding Claim 6, in paragraphs 0112, 0113, 0140 and 0141 and Fig. 7 of Kim and paragraphs 0134, 0147 0166 and Fig.7 of Lin et al, wherein the display element layer further comprises a common connection electrode disposed on the first bank and the common electrode, and connected to the second cathode electrode.
Regarding Claim 7, in paragraphs 0112, 0113, 0140 and 0141 and Fig. 7 of Kim and paragraphs 0134, 0147 0166 and Fig.7 of Lin et al, wherein the common connection electrode is spaced apart from the first reflective electrode.
Regarding Claim 8, in paragraphs 0112, 0113, 0140 and 0141 and Fig. 7 of Kim and paragraphs 0134, 0147 0166 and Fig.7 of Lin et al 8, wherein the common connection electrode is connected in common to the plurality of sub-pixel circuits.
Regarding Claim 9, in paragraphs 0112, 0113, 0140 and 0141 and Fig. 7 of Kim and paragraphs 0134, 0147 0166 and Fig.7 of Lin et al, wherein the second cathode electrode is connected in common to the plurality of sub-pixel circuits.
Regarding Claim 10, in paragraphs 0112, 0113, 0140 and 0141 and Fig. 7 of Kim wherein the first light emitting element includes an n-type semiconductor layer and a p-type semiconductor layer, the first bonding electrode is connected to the p-type semiconductor layer of the first light emitting element, and the second bonding electrode is connected to the n-type semiconductor layer of the first light emitting element.
Regarding Claim 11, in paragraphs 0112, 0113, 0140 and 0141 and Fig. 7 of Kim, wherein the second light emitting element includes an n-type semiconductor layer and a p-type semiconductor layer, the third bonding electrode is connected to the p-type semiconductor layer of the second light emitting element, and the fourth bonding electrode is connected to the n-type semiconductor layer of the second light emitting element.
Regarding Claim 12, in Figs. 6 and 7, Kim method of fabricating a display device, the method comprising: preparing a substrate; forming a pixel circuit layer on the substrate; and forming a display element layer on the pixel circuit layer, wherein the forming of the display element layer comprises: forming a first bank including a first opening; disposing a first light emitting element in the first opening; Kim et al. fail to disclose the limitation on the first bank, forming a second bank including a second opening at least partially overlapping the first opening in a vertical direction; and disposing a second light emitting element in the second opening, and the first light emitting element and the second light emitting element are connected in series to each other. However, Lin et al. discloses a display device where in Figs 6 and 7 and paragraphs 0063 and 0067 the required limitation is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required, limitation in Kim as taught by Lin et al. in order to have compact display device.
Regarding Claim 13, in paragraphs 0112, 0113, 0140 and 0141 and Fig. 7 of Kim, , wherein the forming of the display element layer comprises: forming a first contact hole in a first insulating layer of the pixel circuit layer; and forming a first anode electrode, a first cathode electrode, and a common electrode on the first insulating layer, and the first anode electrode overlaps the first contact hole.
Regarding Claim 14, in paragraphs 0112, 0113, 0140 and 0141 and Fig. 7 of Kim, wherein the forming of the display element layer further comprises: forming a first reflective electrode disposed on the first bank and the first anode electrode, a second reflective electrode disposed on the first bank and the first cathode electrode, and a common connection electrode disposed on the first bank and the common electrode.
Regarding Claim 15, in paragraphs 0112, 0113, 0140 and 0141 and Fig. 7 of Kim, wherein the disposing of the first light emitting element comprises: disposing a first bonding electrode of the first light emitting element on the first reflective electrode, and disposing a second bonding electrode of the first light emitting element on the second reflective electrode.
Regarding Claim 16, in paragraphs 0112, 0113, 0140 and 0141 and Fig. 7 of Kim, 6, wherein the forming of the display element layer comprises: forming a second insulating layer on the first light emitting element; and forming, in the second insulating layer, a second contact hole through which the second reflective electrode is exposed, and a third contact hole through which the common connection electrode is exposed.
Regarding Claim 17, in paragraphs 0112, 0113, 0140 and 0141 and Fig. 7 of Kim, wherein the forming of the display element layer further comprises forming a second anode electrode and a second cathode electrode on the second insulating layer, the second anode electrode overlaps the second contact hole, and the second cathode electrode overlaps the third contact hole.
Regarding Claim 18, in paragraphs 0112, 0113, 0140 and 0141 and Fig. 7 of Kim and paragraphs 0134, 0147 0166 and Fig.7 of Lin et al, 18, wherein the disposing of the second light emitting element comprises: disposing a third bonding electrode of the second light emitting element on the second anode electrode, and disposing a fourth bonding electrode of the second light emitting element on the second cathode electrode.
Regarding Claim 19, in paragraphs 0112, 0113, 0140 and 0141 and Fig. 7 of Kim and paragraphs 0134, 0147 0166 and Fig.7 of Lin et al, wherein the second cathode electrode is connected in common to a plurality of sub-pixel circuits.
Regarding Claim 20, in paragraphs 0112, 0113, 0140 and 0141 and Fig. 7 of Kim and paragraphs 0134, 0147 0166 and Fig. 7 of Lin et al, wherein the common electrode is connected in common to the plurality of sub-pixel circuits.
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 9/10/2026
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