Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gao (US20150006097A1).
Regarding claim 16, Gao teaches a method (paragraph [0014] discloses a method of measuring performance metrics) comprising:
generating a first amount of illumination light by an illumination source (paragraph [0045] discloses the illuminator 102 is configured to generate illumination to a thin film disposed on a semiconductor wafer);
directing the first amount of illumination light to a first measurement site on a surface of a semiconductor wafer during a first measurement instance (paragraph [0045] discloses the illuminator 102 is configured to generate and direct illumination to a thin film disposed on a semiconductor wafer), the semiconductor wafer processed through a first process step of a plurality of process steps of a semiconductor fabrication process flow from bare wafer to an electrical interconnect metallization process step (paragraphs [0036]-[0039] describe the measurement and analysis of the wafer being performed before and after each or certain process steps, including the beginning step and a metallization process step), wherein a first instance of one or more structures under measurement is located at the first measurement site (paragraph [0045] discloses the structure as a thin film);
detecting a first amount of light collected from the surface of the semiconductor wafer in response to the first amount of illumination light (paragraph [0045] discloses the spectrometer 104 is configured to receive illumination reflected from the surface of the semiconductor wafer);
generating a first set of output signals indicative of the detected light during the first measurement instance (paragraph [0046] discloses the spectrometer 104 gathers and sends output signals to be analyzed by a computing system); and
determining an estimated value of an electrical performance metric based at least in part on the first set of output signals (paragraph [0047] discloses the computing system may use data from the spectrometer to determine a characteristic indicative of an electric performance), the estimated value of the electrical performance metric indicative of an expected electrical performance of a semiconductor device including the one or more structures under measurement as if the semiconductor wafer were processed through the plurality of process steps of the semiconductor fabrication process flow (paragraph [0053] discloses the measurement data of the unfinished wafer may be used to predict final device performance. The examiner is interpreting the final device to be a wafer which has finished the fabrication process).
Regarding claim 17, Gao teaches the invention as described above in claim 16 and further teaches generating a second amount of illumination light directed to the first measurement site on the surface of the semiconductor wafer during a second measurement instance, the semiconductor wafer processed through a second process step of the plurality of process steps (claim 13 discloses the measurements repeated at a second process step; paragraph [0036] discloses measured data taken at any process step; paragraph [0055] discloses measurement data is tagged to identify the process step. The examiner interprets this to mean the illumination and detection is performed at least twice);
detecting a second amount of light collected from the surface of the semiconductor wafer in response to the second amount of illumination light (claim 13 discloses the measurements repeated at a second process step; paragraph [0036] discloses measured data taken at any process step; paragraph [0055] discloses measurement data is tagged to identify the process step. The examiner is interpreting this to mean the illumination, detection is performed at least twice);
generating a second set of output signals indicative of the detected light during the second measurement instance, wherein the determining of the estimated value of the electrical performance metric is based at least in part on the first and second sets of output signals (paragraph [0041] discloses model used to predict the estimated performance metrics is updated at each monitoring step).
Regarding claim 18, Gao teaches the invention as explained above in claim 16, and further teaches determining an updated value of one or more process parameters characterizing the first process step, a process step of the plurality of process steps prior to the first process step, a process step subsequent to the first process step of the plurality of process steps, or any combination thereof, based on the estimated value of the electrical performance metric (paragraph [0043] discloses adjusting subsequent process steps based on the estimated performance metric, such as changing an etching time).
Regarding claim 19, Gao teaches the invention as explained above in claim 16, and further teaches estimating values of one or more parameters of interest characterizing one or more structural features of the one or more structures under measurement based at least in part on the first set of output signals, wherein the determining of the estimated value of the electrical performance metric is based at least in part on the estimated values of the parameters of interest (paragraph [0045] discloses an estimate of an electrical performance metric is based at least in part on a band structure characteristic and a structural characteristic measured by the system).
Regarding claim 20, Gao teaches the invention as explained above in claim 19, and further teaches determining an updated value of one or more process parameters characterizing the first process step, a process step of the plurality of process steps prior to the first process step, a process step subsequent to the first process step of the plurality of process steps, or any combination thereof, based on the estimated value of the electrical performance metric and the estimated values of the one or more parameters of interest (paragraph [0043] discloses adjusting subsequent process steps based on the estimated performance metric and sensitivity parameter based on the estimated physical parameter of interest).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Gao (US20150006097A1) in view of Wang (US20200225151A1).
Regarding claim 1, Gao teaches a measurement system (100, Fig. 1; paragraph [0045]) comprising:
an illumination source (102, Fig. 1) configured to generate a first amount of illumination light directed to a first measurement site on a surface of a semiconductor wafer during a first measurement instance (paragraph [0045] discloses the illuminator 102 is configured to generate and direct illumination to a thin film disposed on a semiconductor wafer), the semiconductor wafer processed through a first process step of a plurality of process steps of a semiconductor fabrication process flow from bare wafer to an electrical interconnect metallization process step (paragraphs [0036]-[0039] describe the measurement and analysis of the wafer is performed before and after each or certain process steps, including the beginning step and a metallization process step), wherein a first instance of one or more structures under measurement is located at the first measurement site (paragraph [0045] discloses the structure as a thin film);
at least one detector (104, Fig. 1), the at least one detector configured to detect a first amount of light collected from the surface of the semiconductor wafer in response to the first amount of illumination light (paragraph [0045] discloses the spectrometer 104 is configured to receive illumination reflected from the surface of the semiconductor wafer) and generate a first set of output signals indicative of the detected light during the first measurement instance (paragraph [0046] discloses the spectrometer gathers and sends output signals to be analyzed by a computing system); and
a computing system (116, Fig. 1) configured to determine an estimated value of an electrical performance metric based at least in part on the first set of output signals (paragraph [0047] discloses the computing system may use data from the spectrometer to determine a characteristic indicative of an electric performance), the estimated value of the electrical performance metric indicative of an expected electrical performance of a semiconductor device including the one or more structures under measurement as if the semiconductor wafer were processed through the plurality of process steps of the semiconductor fabrication process flow (paragraph [0053] discloses the measurement data of the unfinished wafer may be used to predict final device performance. The examiner is interpreting the final device to be a wafer which has finished the fabrication process).
Gao fails to teach the detector having a planar, two-dimensional surface sensitive to incident light.
However, in the same field of endeavor of semiconductor metrology, Wang teaches a measurement system (100, Fig. 1) which includes at least one detector (122, Fig. 1) with a planar, 2D surface sensitive to incident light (paragraph [0039] discloses the detector may be a CCD array, which has a planar, 2D surface).
CCD arrays are well-known in the art and have the advantage of being highly sensitive and precise. A person having ordinary skill in the art would be able to reasonably use the CCD array taught in Wang for the detector taught in Gao to gain the benefits of a highly sensitive and precise detector. Thus, it would be obvious for a person of ordinary skill in the art to combine the system of Gao with the CCD detector having a planar, two-dimensional surface taught in Wang in order to benefit from a highly sensitive and precise detector.
Regarding claim 2, Gao as modified by Wang teaches the invention as explained above in claim 1, and further teaches the illumination source further configured to generate a second amount of illumination light directed to the first measurement site on the surface of the semiconductor wafer during a second measurement instance, the semiconductor wafer processed through a second process step of the plurality of process steps , the at least one detector further configured to detect a second amount of light collected from the surface of the semiconductor wafer in response to the second amount of illumination light and generate a second set of output signals indicative of the detected light during the second measurement instance (Gao: claim 13 discloses the measurements repeated at a second process step; paragraph [0036] discloses measured data taken at any process step; paragraph [0055] discloses measurement data is tagged to identify the process step. The examiner is interpreting this to mean the illumination, detection is performed at least twice), wherein the determining of the estimated value of the electrical performance metric is based at least in part on the first and second sets of output signals (Gao: paragraph [0041] discloses model used to predict the estimated performance metrics is updated at each monitoring step).
Regarding claim 3, Gao as modified by Wang teaches the invention as explained above in claim 1, and further teaches determining an updated value of one or more process parameters characterizing the first process step, a process step of the plurality of process steps prior to the first process step, a process step subsequent to the first process step of the plurality of process steps, or any combination thereof, based on the estimated value of the electrical performance metric (Gao: paragraph [0043] discloses adjusting subsequent process steps based on the estimated performance metric, such as changing an etching time).
Regarding claim 4, Gao as modified by Wang teaches the invention as explained above in claim 1, and further teaches estimating values of one or more parameters of interest characterizing one or more structural features of the one or more structures under measurement based at least in part on the first set of output signals, wherein the determining of the estimated value of the electrical performance metric is based at least in part on the estimated values of the parameters of interest (Gao: paragraph [0045] discloses an estimate of an electrical performance metric is based at least in part on a band structure characteristic and a structural characteristic measured by the system).
Regarding claim 5, Gao as modified by Wang teaches the invention as explained above in claim 4, and further teaches determining an updated value of one or more process parameters characterizing the first process step, a process step of the plurality of process steps prior to the first process step, a process step subsequent to the first process step of the plurality of process steps, or any combination thereof, based on the estimated value of the electrical performance metric and the estimated values of the one or more parameters of interest (Gao: paragraph [0043] discloses adjusting subsequent process steps based on the estimated performance metric and sensitivity parameter based on the estimated physical parameter of interest).
Regarding claim 6, Gao as modified by Wang teaches the invention as explained above in claim 1, and further teaches the semiconductor device is a logic device (Gao: paragraph [0031] discloses the wafer may be a logic gate), and wherein the electrical performance metric is any of a drive current, a threshold voltage, a carrier mobility, a current leakage, and a breakdown voltage (Gao: paragraph [0040] discloses the electrical performance metric may be a leakage current or threshold voltage).
Regarding claim 9, Gao as modified by Wang teaches the invention as explained above in claim 1, and further teaches the one or more structures under measurement are fabricated in-die (Gao: paragraphs [0091], [0092]).
Regarding claim 21, Gao teaches a measurement system (100, Fig. 1; paragraph [0045]) comprising:
an illumination source (102, Fig. 1) configured to generate a first amount of illumination light directed to a first measurement site on a surface of a semiconductor wafer during a first measurement instance (paragraph [0045] discloses the illuminator 102 is configured to generate and direct illumination to a thin film disposed on a semiconductor wafer), the semiconductor wafer processed through a first process step of a plurality of process steps of a semiconductor fabrication process flow from bare wafer to an electrical interconnect metallization process step (paragraphs [0036]-[0039] describe the measurement and analysis of the wafer is performed before and after each or certain process steps, including the beginning step and a metallization process step), wherein a first instance of one or more structures under measurement is located at the first measurement site (paragraph [0045] discloses the structure as a thin film);
at least one detector (104, Fig. 1), the at least one detector configured to detect a first amount of light collected from the surface of the semiconductor wafer in response to the first amount of illumination light (paragraph [0045] discloses the spectrometer 104 is configured to receive illumination reflected from the surface of the semiconductor wafer) and generate a first set of output signals indicative of the detected light during the first measurement instance (paragraph [0046] discloses the spectrometer gathers and sends output signals to be analyzed by a computing system); and
a non-transitory, computer-readable medium storing instructions that , when executed by one or more processors (paragraph [0056] discloses a computing system which executes instructions from a memory medium which has at least one processor), causes the one or more processors to:
determine an estimated value of an electrical performance metric based at least in part on the first set of output signals (paragraph [0047] discloses the computing system may use data from the spectrometer to determine a characteristic indicative of an electric performance), the estimated value of the electrical performance metric indicative of an expected electrical performance of a semiconductor device including the one or more structures under measurement as if the semiconductor wafer were processed through the plurality of process steps of the semiconductor fabrication process flow (paragraph [0053] discloses the measurement data of the unfinished wafer may be used to predict final device performance. The examiner is interpreting the final device to be a wafer which has finished the fabrication process).
Gao fails to teach the detector having a planar, two-dimensional surface sensitive to incident light.
However, Wang teaches a measurement system (100, Fig. 1) which includes at least one detector (122, Fig. 1) with a planar, 2D surface sensitive to incident light (paragraph [0039] discloses the detector may be a CCD array, which has a planar, 2D surface).
CCD arrays are well-known in the art and have the advantage of being highly sensitive and precise. A person having ordinary skill in the art would be able to reasonably use the CCD array taught in Wang for the detector taught in Gao to gain the benefits of a highly sensitive and precise detector. Thus, it would be obvious for a person of ordinary skill in the art to combine the system of Gao with the CCD detector having a planar, two-dimensional surface taught in Wang in order to benefit from a highly sensitive and precise detector.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Gao (US20150006097A1) in view of Wang (US20200225151A1) as applied to claim 1 above, and further in view of Golani (US20220113129A1).
Regarding claim 7, Gao as modified by Wang teaches the invention as explained above in claim 1, and further teaches the electrical performance metric is any of a capacitance (Gao: paragraph [0040] discloses the electrical performance metric may be a capacitance), a read and write speed, and a reliability.
Gao as modified by Wang fails to teach the semiconductor device is a memory device.
However, in the same field of endeavor of semiconductor metrology, Golani teaches a measurement system (200, Fig. 2) which measures a metric of a semiconductor device (250, Fig. 2; paragraph [0122]) which may be a memory device (paragraph [0062]).
Gao discloses memory devices are popular semiconductor devices (paragraph [0003]). A person of ordinary skill in the art would be able to do a simple substitution of the known memory device taught in Golani for the general semiconductor wafer taught in Gao and be able to obtain predictable results as memory devices are frequently-fabricated devices. Thus, a person of ordinary skill in the art prior to the effective filing date would find it obvious to combine the system of Gao as modified by Wang with the semiconductor device being a memory device taught in Golani as it is a well-known and frequently fabricated semiconductor device.
Regarding claim 8, Gao as modified by Wang teaches the invention as explained above in claim 1, but fails to teach the semiconductor device is a gate-all-around transistor.
However, Golani teaches a measurement system (200, Fig. 2) which measures a metric of a semiconductor device (250, Fig. 2; paragraph [0122]) which may be a gate-all-around transistor (paragraph [0062]).
Gao discloses the semiconductor device may be different types of transistor (paragraph [0031]), but does not specifically disclose a gate-all-around transistor. However, gate-all-around transistors are well-known and frequently fabricated in the field. A person of ordinary skill in the art would be able to do a simple substitution of the known gate-all-around transistor taught in Golani for the general semiconductor wafer taught in Gao as modified by Wang and be able to obtain predictable results as memory devices are frequently-fabricated devices. Thus, a person of ordinary skill in the art prior to the effective filing date would find it obvious to combine the system of Gao as modified by Wang with the semiconductor device being a gate-all-around transistor taught in Golani as it is a well-known and frequently fabricated semiconductor device.
Claims 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Gao (US20150006097A1) in view of Wang (US20200225151A1) as applied to claim 1 above, and further in view of Stehle (“Multi-pass spectroscopic ellipsometry,” Thin Solid Films 555, 143–147 (2014).).
Regarding claim 10, Gao as modified by Wang teaches the invention as explained above in claim 1, but fails to teach the illumination source, the at least one detector, and the computing system comprise a Multiple Pass Spectroscopic Ellipsometry (MPSE) metrology system.
However, in the same field of endeavor of optical metrology, Stehle discloses the use of a multiple pass spectroscopic ellipsometry system (title; abstract; page 1, column 2, paragraph 2; Fig. 1).
Stehle discloses a multiple pass spectroscopic ellipsometry setup enhances sensitivity with respect to single pass ellipsometry (page 4, column 2, last paragraph). Thus, it would be obvious for a person of ordinary skill in the art prior to the effective filing date to combine the system of Gao as modified by Wang with the multiple pass spectroscopic ellipsometry system taught in Stehle as a way to enhance sensitivity of the measurements.
Regarding claim 11, Gao as modified by Wang and Stehle teaches the invention as explained above in claim 10, and further teaches one or more reflective optical elements disposed in an optical path (Stehle: 'high reflectivity mirrors' - Fig. 1) between the illumination source (Stehle: 'light source' - Fig. 1) and the at least one detector (Stehle: 'analyzing optics and acquisition' - Fig. 1), wherein the optical path is incident on the surface of the semiconductor wafer more than once (Stehle: Fig. 1 depicts the light being incident on the surface of a sample three times).
As discussed above in claim 10, it would be obvious for a person of ordinary skill in the art prior to the effective filing date to combine the system of Gao as modified by Wang with the multiple pass spectroscopic ellipsometry system taught in Stehle as a way to enhance sensitivity of the measurements.
Regarding claim 12, Gao as modified by Wang and Stehle teaches the invention as explained above in claim 11, and further teaches the one or more reflective optical elements including at least two reflective optical elements (Stehle: 'high reflectivity mirrors' - Fig. 1), the at least two reflective optical elements positioned in the optical path to direct light from the first measurement site back to the first measurement site (Stehle: see Fig. 1, which depicts the mirrors reflecting light back to the sample).
As discussed above in claim 10, it would be obvious for a person of ordinary skill in the art prior to the effective filing date to combine the system of Gao as modified by Wang with the multiple pass spectroscopic ellipsometry system taught in Stehle as a way to enhance sensitivity of the measurements.
Regarding claim 13, Gao as modified by Wang and Stehle teaches the invention as explained above in claim 11, and further teaches the one or more reflective optical elements including a planar reflector having a planar reflective surface disposed over the wafer (Stehle: 'high reflectivity mirrors' - Fig. 1) and facing the wafer surface (Stehle: Fig. 1 depicts the mirrors facing the sample), wherein the planar reflector is positioned in the optical path to direct light from the first measurement site to a second measurement site on the surface of the semiconductor wafer, wherein a second instance of the one or more structures under measurement is located at the second measurement site (Stehle: see Fig. 1, which depicts the light being reflected back onto the sample at least three times at different sites).
As discussed above in claim 10, it would be obvious for a person of ordinary skill in the art prior to the effective filing date to combine the system of Gao as modified by Wang with the multiple pass spectroscopic ellipsometry system taught in Stehle as a way to enhance sensitivity of the measurements.
Regarding claim 14, Gao as modified by Wang and Stehle teaches the invention as explained above in claim 10, and further teaches a second metrology system (Wang: 125, Fig. 1) configured to generate a second set of output signals indicative of a measurement of the one or more structures under measurement (Wang: paragraph [0048] discloses the detector 138 part of the second metrology system produces signals indicative of the structures under measurement), wherein the determining of the estimated value of the electrical performance metric is based on the first and second sets of output signals (Wang: Fig. 1 depicts the signals 123 and 124 from both metrology systems being input into the computing system, which outputs an estimate value 190 indicative of a parameter of interest).
The use of two metrology systems enables multiple types of measurements to be made, therefore having the advantage of enhanced measurements of a structure. Thus, a person of ordinary skill in the art would find it obvious to combine the system of Gao as modified by Wang with the second metrology system taught in Wang in order to benefit from multiple types of measurements, which would enhance the data taken.
Regarding claim 15, Gao as modified by Wang and Stehle teaches the invention as explained above in claim 14, and further teaches the second metrology system is a spectroscopic reflectometer (Wang: paragraph [0103] discloses the reflectometer 125 may be a spectroscopic reflectometer), an angle resolved reflectometer, a x-ray diffractometer, or a Raman spectrometer.
Spectroscopic reflectometers are well-known and widely used in the art. They have the advantage of being rapid and non-destructive. A person of ordinary skill in the art would find it obvious to use the spectroscopic reflectometer taught in Wang as the second metrology system taught in Gao as modified by Wang to benefit from the rapid and non-destructive measurements. Thus, it would be obvious for a person of ordinary skill in the art prior to the effective filing date to combine the system of Gao as modified by Wang with the spectroscopic reflectometer taught in Wang in order to benefit from rapid and non-destructive measurements.
Conclusion
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/ALEXANDRIA MENDOZA/Examiner, Art Unit 2877
/MICHELLE M IACOLETTI/Supervisory Patent Examiner, Art Unit 2877
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