DETAILED ACTION
This Office Action is in response to Applicant’s application 18/888,460 filed on September 18, 2024 in which claims 1 to 14 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on September 18, 2024 have been reviewed and accepted by the Examiner.
Information Disclosure Statement
The Information Disclosure Statements (IDS), filed on July 8, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Notation
References to patents will be in the form of [C:L] where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of [xxxx].
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-3 and 5-10 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of co-pending Application No. 18/917,524 (‘524) in view of U.S. 2026/013227 (Kim).
This is a provisional nonstatutory double patenting rejection. Examiner notes the self-styled divisional status of the instant application. Examiner notes that the ‘524 application is unexamined and therefore not subject to restriction. Consequently, the safe harbor provisions of 35 U.S.C. § 121 do not apply.
Table 1 – Comparison of Pending Claims to ‘524 Claims
Pending Claim
‘524 Claim
1. A semiconductor device, comprising:
a gate structure disposed over a semiconductor substrate;
a dielectric layer surrounding the gate structure;
a source region and a drain region disposed in the semiconductor substrate and on opposite sides of the gate structure;
a first dipole portion disposed over the semiconductor substrate and covering the source region; and
a first dielectric spacer disposed over the first dipole portion and adjacent to the dielectric layer.
1. A semiconductor device, comprising:
a gate structure disposed over a semiconductor substrate;
a source region and a drain region disposed in the semiconductor substrate and on opposite sides of the gate structure;
a first lightly doped region disposed in the semiconductor substrate and extending from the source region to the gate structure;
a first dipole portion disposed over the semiconductor substrate and covering the source region and the first lightly doped region; and
a first dielectric spacer covering the first dipole portion.
9. The semiconductor device of claim 1, further comprising:
a first dielectric layer covering the gate structure,
wherein the first dielectric spacer is separated from the gate structure by the first dielectric layer.
2. The semiconductor device of claim 1, wherein a top surface of the gate structure is covered by the dielectric layer.
Kim teaches
3. The semiconductor device of claim 1, wherein the dielectric layer and the first dielectric spacer include different materials.
Kim teaches
5. The semiconductor device of claim 1, further comprising:
a source contact penetrating through the first dipole portion to directly contact the source region.
4. The semiconductor device of claim 1, further comprising:
a source contact penetrating through the first dipole portion to directly contact the source region,
wherein the source contact is separated from the first dielectric spacer.
6. The semiconductor device of claim 1, further comprising:
a first lightly doped region disposed in the semiconductor substrate and extending from the source region to the gate structure.
From claim 1
a first lightly doped region disposed in the semiconductor substrate and extending from the source region to the gate structure
7. The semiconductor device of claim 6, wherein
the first lightly doped region is in direct contact with the first dipole portion.
3. The semiconductor device of claim 1, wherein
the first lightly doped region is in direct contact with the first dipole portion.
8. The semiconductor device of claim 6, wherein
the first lightly doped region is separated from the first dielectric spacer by the first dipole portion.
7. The semiconductor device of claim 1, wherein
the first lightly doped region is separated from the first dielectric spacer by the first dipole portion.
9. The semiconductor device of claim 6, further comprising:
a first halo implant region disposed in the semiconductor substrate and extending from the source region to the gate structure,
wherein the first lightly doped region is disposed over the first halo implant region.
5. The semiconductor device of claim 1, further comprising:
a first halo implant region disposed below the first lightly doped region, wherein the first lightly doped region and the first halo implant region have different conductivity types.
10. The semiconductor device of claim 1, further comprising:
a second dipole portion disposed over the semiconductor substrate and covering the drain region, wherein
a material of the first dipole portion is the same as a material of the second dipole portion.
12. The semiconductor device of claim 11, further comprising:
a second lightly doped region disposed in the semiconductor substrate and extending from the drain region to the gate structure; and
a second dipole portion disposed over the semiconductor substrate and covering the drain region and the second lightly doped region, wherein the drain region is separated from the second dielectric layer by the second dipole portion.
13. The semiconductor device of claim 12, wherein
a material of the first dipole portion is the same as a material of the second dipole portion.
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Regarding claim 1 and referring to Table 1, Examiner observes that claim 1 of the ‘524 patent does not teach a dielectric layer surrounding the gate structure. Examiner notes that claim 9 of the ‘524 patent teaches this structure is a useful modification of the device of claim 1.
Kim is directed to transistors using dielectric layers. Kim teaches at Figure 1 a dielectric layer, 310 [0057-58], surrounding the gate structure, 233 [0057-58] which is useful to form the source/drain ohmic contacts.
Taken as a whole the prior art is directed to improvements in transistors. Kim teaches that a dielectric layer surrounding the gate facilitates fabrication of the source/drain contacts.
Accordingly it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 1 with a dielectric layer surrounding the gate structure to facilitate the formation of source/drain contacts and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 2 which depends upon claim 1, Kim teaches a top surface of the gate structure is covered by the dielectric layer at Figure 1.
Regarding claim 3 which depends upon claim 1, Kim teaches the dielectric layer, 310 is silicon nitride at [0057] and teaches a first dielectric spacer, 251 [0052] is silicon oxide which are include different materials. Examiner notes that this relationship of spacer to etch stop is well known known in the art.
Regarding claim 5 which depends upon claim 1, claim 4 of the ‘524 Application teaches this subject matter.
Regarding claim 6 which depends upon claim 1, claim 1 of the ‘524 Application teaches this subject matter.
Regarding claim 7 which depends upon claim 1, claim 3 of the ‘524 Application teaches this subject matter.
Regarding claim 8 which depends upon claim 1, claim 7 of the ‘524 Application teaches this subject matter.
Regarding claim 9 which depends upon claim 6, because the LDD extends from the source to gate, it follows that the halo implant also extend from the source to gate because the halo is implanted below the LDD in claim 5 of the ‘524 application. Likewise LDD over a halo described the structure of a halo disposed below the LDD. Thus claim 5 of the ‘524 application describes the subject matter of pending claim 9.
Regarding claim 10 which depends upon claim 1, claims 12/10 describe this subject matter.
Allowable Subject Matter
Claims 4 and 11-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4 the prior art fails to disclose the device of claim 1, wherein the first dielectric spacer is separated from the source region by the first dipole portion.
Regarding claim 11 the prior art fails to disclose the device of claim 10, further comprising a drain contact penetrating through the second dipole portion to directly contact the drain portion.
Regarding claim 12 the prior art fails to disclose the device of claim 10, further comprising: a second dielectric spacer disposed over the second dipole portion and adjacent to the dielectric layer, wherein the second dielectric spacer is separated from the drain region by the second dipole portion.
Regarding claim 13 the prior art fails to disclose the device of claim 10, further comprising: a second lightly doped region disposed in the semiconductor substrate and extending from the drain region to the gate structure, wherein the second lightly doped region is in direct contact with the second dipole portion.
Claim 14 depends upon claim 13 and is allowable on that basis.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed on the notice of references cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.E. Schoenholtz/Primary Examiner, Art Unit 2893
Prosecution Insights