Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 18-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation " the semiconductive layer " in line 1. There is insufficient antecedent basis for this limitation in the claim. For the purposes of Examination, this limitation will be interpreted as “the active layer”, which has a precedence in claim 1.
Claim 19 recites the limitation " the semiconductive layer " in line 1. There is insufficient antecedent basis for this limitation in the claim. For the purposes of Examination, this limitation will be interpreted as “the active layer”, which has a precedence in claim 1.
Claim 20 recites the limitation " the carrier substrate" in line 1. There is insufficient antecedent basis for this limitation in the claim. For the purposes of Examination, this limitation will be interpreted as “the semiconductor substrate”, which has a precedence in claim 1.
Furthermore, the preambles of claims 18-20 recite “The substrate of claim 1”. There is insufficient antecedent basis for this limitation in the claim. For the purposes of Examination, this limitation will be interpreted as “the structure of claim 1”, which has a precedence in the preamble of claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Henley et al. (US 20040097055 A1; hereinafter “Henley”).
In re claim 11, Henley discloses, in figs. 1-12, a structure, comprising:
a carrier substrate 1205 (¶61);
an electrically insulating layer 1203 overlying the carrier substrate 1205 and a trapping layer 1103 (a trapping layer 1103 is formed at the location A; ¶59-61),
the trapping layer 1103 comprising cavities therein (gettering layer 1103 is formed by implanting helium ions creating pockets or microbubbles, which provide trapping sites for impurities in the gettering layer; ¶34-36, 59);
a semiconductive layer 809 overlying the electrically insulating layer 1203 (figs. 11-12; ¶ 55, 59); and
a plurality of electrically isolating trenches 1209 extending vertically through the semiconductive layer 809 to the electrically insulating layer 1203 (¶61).
In re claim 12, Henley discloses, in figs. 1-12, the structure of claim 11, wherein the electrically insulating layer 1203 (705 in fig. 11) consists of silicon oxide (¶ 0032, 0052-0053).
In re claim 13, Henley discloses, in figs. 1-12, the structure of claim 11, wherein the electrically insulating layer 1203 (705 in fig. 11) comprises a stack of dielectric and/or metal materials (¶ 0032, 0052-0053).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-7, 10, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20060175613 A1; hereinafter “Lee”) in view of Henley et al. (US 20040097055 A1; hereinafter “Henley”).
In re claim 1, Lee discloses, in fig. 6, a structure for an image sensor (¶37), comprising:
a semiconductor substrate (10, 20, 30) comprising a trapping layer 30 (¶29, 30-33),
the trapping layer 30 including cavities therein (¶30-33);
an active layer 40, 42 (¶35, 38) overlying the trapping layer 30; and
a plurality of electrically isolating trenches 46 extending vertically extending through an upper portion of the active layer 40, 42 to the electrically insulating layer.
Lee does not expressly disclose the structure is for a front-side image sensor,
an electrically insulating layer overlying the semiconductor substrate;
the active layer overlying the electrically insulating layer;
the plurality of electrically isolating trenches extending vertically through the active layer to the electrically insulating layer,
the plurality of electrically isolating trenches defining a plurality of pixels.
In the same field of endeavor, Henley discloses, in figs. 1-12 (¶59-61), a structure, comprising:
an electrically insulating layer 1203 overlying a semiconductor substrate 1205;
the active layer 809 overlying the electrically insulating layer 1205;
the plurality of electrically isolating trenches 1209 extending vertically through the active layer 809 to the electrically insulating layer 1203.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings Hanley into the structure of Lee in order to better device isolation and reduce crosstalk.
The combined teachings Lee and Hanley disclose the plurality of electrically isolating trenches defining a plurality of pixels.
Regarding the claim limitation “the image sensor structure is for a front-side image sensor”: claim 1 is directed to a structure, not to a method of operating and/or using the structure. Since Lee as modified by Hanley discloses all the structural limitations of the structure recited in claim 1, the method of operating and/or using the structure of claim 1 does not distinguish it from the image sensor device taught by Lee as modified by Hanley.
MPEP § 2114-II states that a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990).
In re claim 2, Lee as modified by Hanley discloses the structure of claim 1.
Lee further discloses, in fig. 6, wherein the trapping layer 30 is buried within the semiconductor substrate.
In re claim 3, Lee as modified by Hanley discloses the structure of claim 1, wherein the trapping layer (Lee: 30) is in direct contact with the electrically insulating layer (Hanley: 1203).
In re claim 4, Lee as modified by Hanley discloses the structure of claim 1.
Lee further discloses, in fig. 6, wherein a density of the cavities within the trapping layer 30 is higher than or equal to 1015 cavities/cm3 (e.g., 1E18 to 1E21 atoms/cc; ¶11, 33).
In re claim 6, Lee as modified by Hanley discloses the structure of claim 1.
Lee further discloses, in fig. 6, wherein the active layer 42 comprises a doped-semiconductor material (e.g., p-doped).
In re claim 7, Lee as modified by Hanley discloses the structure of claim 1.
Lee further discloses, in fig. 6, wherein the active layer comprises:
a first semiconductive layer 40; and
a second semiconductive layer 42 overlying the first semiconductive layer 40,
the second semiconductive layer 42 exhibiting substantially similar lattice parameters and coefficients of thermal expansion to the first semiconductive layer 40 (¶35-38).
In re claim 10, Lee as modified by Hanley discloses the structure of claim 1.
Henley further discloses, in figs. 1-12, wherein the electrically insulating layer 1203 (705 in fig. 11) comprises silicon oxide (¶ 0032, 0052-0053).
In re claim 18 (as best understood), Lee as modified by Hanley discloses the substrate of claim 1.
Lee further discloses, in fig. 6, wherein the semiconductive layer 42 comprises a doped-semiconductor material (e.g., p-doped) (¶38).
In re claim 19 (as best understood), Lee as modified by Hanley discloses the substrate of claim 1.
Lee further discloses, in fig. 6, wherein the semiconductive layer 42 comprises a silicon layer (¶35, 38).
In re claim 20 (as best understood), Lee as modified by Hanley discloses the substrate of claim 1.
Lee further discloses, in fig. 6, wherein the carrier substrate (10, 20, 30) comprises a semiconductor material (¶29).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Henley and further in view of Kadono et al. (US 20210083058 A1; hereinafter “Kadono”).
In re claim 5, Lee as modified by Hanley discloses the structure of claim 1.
Lee as modified by Hanley does not expressly disclose wherein the semiconductor substrate comprises monocrystalline silicon.
In the same field of endeavor, Kadono discloses, in figs. 1A-1C, an SOI substrate for a solid-state imaging device, wherein a semiconductor substrate 10 comprises monocrystalline silicon (¶35).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Kadono into the device of Lee as modified by Henley in order to obtain an epitaxial silicon wafer having high gettering capability resulting in even more reduced white spot defects (¶6-7, 35-36 of Kadono).
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Henley and further in view of Doi et al. (JP 2011014673 A; hereinafter “Doi”).
In re claim 8, Lee as modified by Hanley discloses the structure of claim 1.
Lee as modified by Hanley does not expressly disclose wherein a thickness of the electrically insulating layer is between 5 nm and 400 nm.
In the same field of endeavor, Doi discloses, in figs. 4a-4e, a SOI substrate, wherein a thickness of the electrically insulating layer 205 is 5 nm and 400 nm (“In this embodiment, the film thickness of the silicon nitride film is 50 nm and the film thickness of the second silicon oxide film is 5 nm. However, the present invention is not limited to this. For example, as in the first embodiment, the thickness of the silicon nitride film 203 is, for example, in the range of 40 nm to 65 nm, and the thickness of the second silicon oxide film 204 is, for example, in the range of more than 0 nm to 25 nm or less. The same effect can be obtained”) (page 7, 4th-6th paragraphs).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Doi into the device of Lee as modified by Henley in order to maintain the isolation of the device layer from the carrier substrate.
In re claim 9, Lee as modified by Hanley discloses the structure of claim 1.
Lee as modified by Hanley does not expressly disclose wherein a thickness of the electrically insulating layer is between 30 nm and 150 nm.
In the same field of endeavor, Doi discloses, in figs. 4a-4e, a SOI substrate, wherein a thickness of the electrically insulating layer 205 is 30 nm and 150 nm (“In this embodiment, the film thickness of the silicon nitride film is 50 nm and the film thickness of the second silicon oxide film is 5 nm. However, the present invention is not limited to this. For example, as in the first embodiment, the thickness of the silicon nitride film 203 is, for example, in the range of 40 nm to 65 nm, and the thickness of the second silicon oxide film 204 is, for example, in the range of more than 0 nm to 25 nm or less. The same effect can be obtained”) (page 7, 4th-6th paragraphs).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Doi into the device of Lee as modified by Henley in order to maintain the isolation of the device layer from the carrier substrate.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Henley et al. (US 20040097055 A1; hereinafter “Henley”) in view of Doi et al. (JP 2011014673 A; hereinafter “Doi”).
In re claim 14, Henley discloses, in figs. 1-12, the structure of claim 11 outlined above.
Henley does not expressly disclose wherein the electrically insulating layer comprises an upper silicon oxide layer, a lower silicon oxide layer, and a silicon nitride layer positioned between the upper silicon oxide layer and the lower silicon oxide layer.
In the same field of endeavor, Doi discloses, in figs. 4a-4e, a SOI substrate, wherein the electrically insulating layer 205 comprises an upper silicon oxide layer 204, a lower silicon oxide layer 202, and a silicon nitride layer 203 positioned between the upper silicon oxide layer 204 and the lower silicon oxide layer 202 (page 6, 4th-8th paragraphs).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Doi into the device of Henley in order to maintain the isolation of the device layer from the carrier substrate.
In re claim 15, Henley modified by Doi discloses the structure of claim 14 outlined above.
Doi further disclose, in figs. 4a-4e (page 7, 4th-6th paragraphs), wherein:
a thickness of the upper silicon oxide layer 204 is between 5 nm and 50 nm (“the film thickness of the second silicon oxide film is 5 nm”),
a thickness of the silicon nitride layer 203 is between 10 nm and 100 nm (“the film thickness of the silicon nitride film is 50 nm”), and
a thickness of the lower silicon oxide layer 202 is between 50 nm and 500 nm (e.g., 200 nm).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Henley et al. (US 20040097055 A1; hereinafter “Henley”) in view of Takizawa et al. (US 20100090303 A1; hereinafter “Takizawa”).
In re claim 16, Henley discloses, in figs. 1-12, the structure of claim 11 outlined above.
Henley does not expressly disclose wherein the electrically insulating layer comprises a first dielectric layer, a second dielectric layer, and a metal layer positioned between the first dielectric layer and the second dielectric layer.
In the same field of endeavor, Takizawa discloses, in fig. 1 (¶76-81), an SOI substrate, wherein the electrically insulating layer (12, 15) comprises a first dielectric layer (e.g., middle portion of layer 12), a second dielectric layer (e.g., right portion of layer 12), and a metal layer 15 (a damaged layer formed of tin or aluminum; ¶79-80) positioned between the first dielectric layer and the second dielectric layer.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Takizawa into the device of Henley such that the metal (for example, a metal contaminant) in upper device layer passes readily through the silicon oxide layer and an SOI substrate with a high gettering ability can be advantageously provided (¶83-85 of Takizawa).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Henley et al. (US 20040097055 A1; hereinafter “Henley”) in view of Inoue et al. (US 20130248862 A1; hereinafter “Inoue”) and Meynants et al. (US 20200194474 A1; hereinafter “Meynants”).
In re claim 17, Henley discloses, in figs. 1-12, the structure of claim 11.
Henley does not expressly disclose the semiconductive layer defines an active layer of an image sensor, and the plurality of electrically isolating trenches defines a plurality of pixels.
In the same field of endeavor, Inoue discloses, in figs. 6-12, an image sensor formed on an SOI substrate 300,
wherein a semiconductive layer 31A defines an active layer of an image sensor, and the plurality of electrically isolating trenches defines a plurality of pixels (¶37, 66).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Inoue into the structure of Henley and make the semiconductor layer part of an image sensor. One would have been motivated to do so as Meynants et al. (US 20200194474 A1) teaches forming image sensor in an epitaxial layer grown on a silicon-on-insulator (SOI) wafer has the benefit of improved thickness uniformity control during the backside thinning process (¶ 0054-0058 and fig. 2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
