Prosecution Insights
Last updated: October 01, 2026
Application No. 18/889,666

PACKAGE SUBSTRATE INCLUDING FIBER-REINFORCED DIELECTRIC LAYER, PACKAGE STRUCTURE INCLUDING THE PACKAGE SUBSTRATE AND METHOD OF FORMING THE SAME

Non-Final OA §102§103
Filed
Sep 19, 2024
Priority
Jun 07, 2024 — provisional 63/657,676
Examiner
FARMER, EMILY NICOLE
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
43 granted / 48 resolved
+29.6% vs TC avg
Moderate +6% lift
Without
With
+6.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
18 currently pending
Career history
59
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
62.1%
+22.1% vs TC avg
§102
23.2%
-16.8% vs TC avg
§112
11.1%
-28.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 48 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of Claims Claims 1-20 are pending. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4, 6-8, 10, 11, 13, 15, 16, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Blackshear et al. (US PGPub 2009/0155552; herein known as Blackshear). Regarding claim 1, Blackshear teaches (Fig. 2) a package substrate, comprising: a core (102, [0015]); a first dielectric layer (106, [0013]) on a first side (108, top) of the core; a second dielectric layer (106, [0013]) on a second side (110, bottom) of the core opposite the first side of the core; and a fiber-reinforced dielectric layer (120A, 120B, [0014]) on at least one of the first side of the core or the second side of the core. Regarding claim 2, Blackshear teaches (Fig. 2) the package substrate of claim 1, wherein the fiber-reinforced dielectric layer (120A, 120B, [0014]) comprises a dielectric material (epoxy or ABF material, [0015]) and a fiber sheet (glass cloth, [0016]) embedded in the dielectric material ([0016]). Regarding claim 3, Blackshear teaches (Fig. 2) the package substrate of claim 2, wherein the fiber sheet comprises an inorganic material including at least one of glass, SiO2, Al2O3, Ca, B, or Mg (glass, [0016]). Regarding claim 4, Blackshear teaches (Fig. 2) the package substrate of claim 2, wherein the fiber sheet comprises a woven fiber sheet (glass cloth, [0016]). Regarding claim 6, Blackshear teaches (Fig. 2) the package substrate of claim 1, wherein the fiber-reinforced dielectric layer comprises: an upper fiber-reinforced dielectric layer (120A, [0014]) on the first side of the core (108, top); and a lower fiber-reinforced dielectric layer (120B, [0014) on the second side of the core (110, bottom). Regarding claim 7, Blackshear teaches (annotated Fig. 2 below) the package substrate of claim 6, wherein the upper fiber-reinforced dielectric layer (120A, [0014] is located on an upper surface of the first dielectric layer (106, [0013]) and further includes a fiber sheet (glass cloth, [0016]) and plurality of upper metal vias (UV, [0015]) extending through the fiber sheet (see figure). PNG media_image1.png 326 618 media_image1.png Greyscale Regarding claim 8, Blackshear teaches (Fig. 2) the package substrate of claim 7, wherein the first dielectric layer (106, [0013]) comprises a plurality of first metal interconnect structures (104, [0015]), and the plurality of upper metal vias are electrically coupled to the plurality of first metal interconnect structures (copper connection structures are shown to extend through 106 and 120A and are disclosed to electrically couple the core to external structures, [0017]). Regarding claim 10, Blackshear teaches (annotated Fig. 2 below) the package substrate of claim 6, wherein the lower fiber-reinforced dielectric layer (120B, [0016]) is located on a lower surface (110, bottom) of the second dielectric layer (106, [0013]) and further includes a fiber sheet (glass cloth, [0016]) and a plurality of lower metal vias (LV, [0015]) extending through the fiber sheet (see figure). PNG media_image1.png 326 618 media_image1.png Greyscale Regarding claim 11, Blackshear teaches (Fig. 2) the package substrate of claim 10, wherein the second dielectric layer (106, [0013]) comprises a plurality of second metal interconnect structures (104, [0015]), and the plurality of lower metal vias are electrically coupled to the plurality of second metal interconnect structures (copper connection structures are shown to extend through 106 and 120B and are disclosed to electrically couple the core to a lower ball grid array for package connection, [0017]). Regarding claim 13, Blackshear teaches (annotated Fig. 2 below) a package structure, comprising: a package substrate (90), comprising: a core (102, [0015]) including a plurality of through vias (TV); and an upper fiber-reinforced dielectric layer (120A, [0016]) on a first side of the core (108, top), comprising a plurality of upper metal vias (annotated Fig. 2 above, UV, [0015]) electrically coupled to the plurality of through vias ([0017]); and a semiconductor module (92, [0017]) attached to the package substrate on the first side of the core, and comprising a plurality of solder bumps (140, [0017]) contacting the plurality of upper metal vias, respectively. PNG media_image2.png 354 622 media_image2.png Greyscale Regarding claim 15, Blackshear teaches (annotated Fig. 2 above) the package structure of claim 13, further comprising: a lower fiber-reinforced dielectric layer (120B, [0016]) on a second side of the core (110, bottom), comprising a plurality of lower metal vias (annotated Fig. 2 below, LV, [0015]); and a ball grid array (BGA) attached to the package substrate on the second side of the core and electrically coupled to the plurality of through vias in the core through the plurality of lower metal vias. PNG media_image1.png 326 618 media_image1.png Greyscale Regarding claim 16, Blackshear teaches (Fig. 2) the package structure of claim 15, further comprising: a first dielectric layer (106, [0014]) between the core (102) and the upper fiber-reinforced dielectric layer (120A); and a second dielectric layer (106, [0014]) between the core (102) and the lower fiber-reinforced dielectric layer (120B). Regarding claim 18, Blackshear teaches (Fig. 2) the package structure of claim 16, wherein the upper fiber-reinforced dielectric layer (120A, [0014]) is on an upper surface (108, top) of the first dielectric layer (106, [0013]) and comprises: a dielectric material (epoxy or ABF material, [0015]); and a fiber sheet (glass cloth, [0016]) in the dielectric material, wherein the plurality of upper metal vias in the dielectric material extend through the fiber sheet (see figure). Regarding claim 19, Blackshear teaches (Fig. 2) the package structure of claim 16, wherein the lower fiber-reinforced dielectric layer (120B, [0014]) is on a lower surface (110, bottom) of the second dielectric layer (106, [0013]) and comprises: a dielectric material (epoxy or ABF material, [0015]); and a fiber sheet (glass cloth, [0016]) in the dielectric material, wherein the plurality of lower metal vias in the dielectric material extend through the fiber sheet (see figure). Regarding claim 20, Blackshear teaches (Fig. 2) a method of forming a package substrate, the method comprising: forming a first dielectric layer (106, [0013]) on a first side (108, top) of a core (102, [0013]); forming a second dielectric layer (106, [0013]) on a second side (110, bottom) of the core opposite the first side of the core; and forming a fiber-reinforced dielectric layer (120A, 120B, [0013]) on at least one of the first side of the core or the second side of the core ([0013]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Blackshear as applied to claims 1 and 13 above, and further in view of Yang et al. (US PGPub 2021/0296221; herein known as Yang). Regarding claim 5, Blackshear teaches (annotated Fig. 2 below) the package substrate of claim 1, further comprising: a die mounting region (DMR); but does not explicitly teach a ring mounting region adjacent the die mounting region; and a separation region between the die mounting region and the ring mounting region, wherein the fiber-reinforced dielectric layer is located in the separation region. PNG media_image3.png 325 616 media_image3.png Greyscale In analogous art, Yang teaches (annotated Fig. 1J below) a ring mounting region (R2, [0019]) adjacent to the die mounting region and a separation region (SR) between the die mounting region (DMR) and the ring mounting region (the separation region is interpreted to be the space between where the die is mounted and where the ring is located). PNG media_image4.png 408 518 media_image4.png Greyscale It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Blackshear and of Yang to include a ring mounting region adjacent to the die mounting region and a separation region between the die mounting region and the ring mounting region in order to provide rigidity to the semiconductor package to prevent warpage (Yang, [0051]). Inclusion of the ring mounting region and separation region of Yang in the embodiment of Blackshear would necessarily result in the fiber-reinforced dielectric layer being located in the separation region, as the fiber-reinforced dielectric layer substantially spans the width of the package. Regarding claim 14, Blackshear teaches the package structure of claim 13, but does not explicitly teach a stiffener ring around the semiconductor module on the package substrate, wherein the package substrate comprises a separation region separating the stiffener ring from the semiconductor module and the upper fiber-reinforced dielectric layer is located in the separation region. In analogous art, Yang teaches (annotated Fig. 1J above) a stiffener ring (200, [0053]) around the semiconductor module (128A,B, [0048]) on the package substrate (10, [0051]) wherein the package substrate comprises a separation region (SR) separating the stiffener ring (200) from the semiconductor module (128A,B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Blackshear and of Yang to include a stiffener ring around the semiconductor module on the package substrate, wherein the package substrate comprises a separation region separating the stiffener ring from the semiconductor module in order to provide rigidity to the semiconductor package to prevent warpage (Yang, [0051]). Inclusion of the stiffener ring and separation region of Yang in the embodiment of Blackshear would necessarily result in the fiber-reinforced dielectric layer being located in the separation region, as the fiber-reinforced dielectric layer substantially spans the width of the package. Claims 9, 12, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Blackshear as applied to claims 6 and 16 above, and further in view of Kuwabara (US PGPub 2024/0339388; herein known as Kuwabara). Regarding claim 9, Blackshear teaches the package substrate of claim 6, but does not explicitly teach wherein the fiber-reinforced dielectric layer further comprises an embedded upper fiber-reinforced dielectric layer embedded in the first dielectric layer. Blackshear does, however, teach wherein the first dielectric layer can be comprised of a fiber-reinforced dielectric layer. In analogous art, Kuwabara teaches (Fig. 1) a fiber-reinforced dielectric layer (11, 21, 31, [0040]) as a part of a stack of dielectric layers. Kuwabara teaches wherein inclusion of layers 11, 21, or 31 as a fiber-reinforced dielectric layer is desirable in order to provide adequate rigidity to the package substrate ([0040]). Additionally, Kuwabara teaches wherein any of the dielectric layers can optionally not include a glass fiber, in order to facilitate formation of fine wirings or to enhance adhesion with other layers ([0040]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Blackshear and of Hu to include wherein the fiber-reinforced dielectric layer further comprises an embedded upper fiber-reinforced dielectric layer embedded in the first dielectric layer in order to reinforce the strength of the dielectric film for easy handling, while allowing for formation of fine wirings and adhesion with overlying layers (Kuwabara, [0040]). Regarding claim 12, Blackshear teaches the package substrate of claim 6, but does not explicitly teach wherein the fiber-reinforced dielectric layer further comprises an embedded lower fiber-reinforced dielectric layer embedded in the second dielectric layer. Blackshear does, however, teach wherein the second dielectric layer can be comprised of a fiber-reinforced dielectric layer. In analogous art, Kuwabara teaches (Fig. 1) a fiber-reinforced dielectric layer (11, 21, 31, [0040]) as a part of a stack of dielectric layers. Kuwabara teaches wherein inclusion of layers 11, 21, or 31 as a fiber-reinforced dielectric layer is desirable in order to provide adequate rigidity to the package substrate ([0040]). Additionally, Kuwabara teaches wherein any of the dielectric layers can optionally not include a glass fiber, in order to facilitate formation of fine wirings or to enhance adhesion with other layers ([0040]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Blackshear and of Hu to include wherein the fiber-reinforced dielectric layer further comprises an embedded lower fiber-reinforced dielectric layer embedded in the first dielectric layer in order to reinforce the strength of the dielectric film for easy handling, while allowing for formation of fine wirings and adhesion with overlying layers (Kuwabara, [0040]). Regarding claim 17, Blackshear teaches the package structure of claim 16, but does not explicitly teach further comprising: an embedded upper fiber-reinforced dielectric layer embedded in the first dielectric layer; and an embedded lower fiber-reinforced dielectric layer embedded in the second dielectric layer. Blackshear does, however, teach wherein the first dielectric layer can be comprised of a fiber-reinforced dielectric layer. In analogous art, Kuwabara teaches (Fig. 1) a fiber-reinforced dielectric layer (11, 21, 31, [0040]) as a part of a stack of dielectric layers. Kuwabara teaches wherein inclusion of layers 11, 21, or 31 as a fiber-reinforced dielectric layer is desirable in order to provide adequate rigidity to the package substrate ([0040]). Additionally, Kuwabara teaches wherein any of the dielectric layers can optionally not include a glass fiber, in order to facilitate formation of fine wirings or to enhance adhesion with other layers ([0040]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Blackshear and of Hu to include an embedded upper fiber-reinforced dielectric layer embedded in the first dielectric layer; and an embedded lower fiber-reinforced dielectric layer embedded in the second dielectric layer in order to reinforce the strength of the dielectric film for easy handling, while allowing for formation of fine wirings and adhesion with overlying layers (Kuwabara, [0040]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EMILY FARMER/Examiner, Art Unit 2812 /DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Sep 19, 2024
Application Filed
Sep 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
96%
With Interview (+6.3%)
3y 0m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 48 resolved cases by this examiner. Grant probability derived from career allowance rate.

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