DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ko et al. (20220344217)
Regarding Claim 1, in paragraphs 0023, 09024, 0025, 0026, 0027, 0047, 0048, 0049 (and especially paragraph 0049), 0050, 0087 and 0088, Ko et al. discloses a method for forming a semiconductor device structure, comprising: forming a plurality of semiconductor nanostructures and a plurality of semiconductor sacrificial nanostructures 106/109 over a substrate 102, wherein the semiconductor nanostructures and the semiconductor sacrificial nanostructures are laid out in an alternating manner; replacing the semiconductor sacrificial nanostructures with dielectric nanostructures; forming inner spacers 132 over side edges of the dielectric nanostructures; and forming an epitaxial structure on side edges of the semiconductor nanostructures and the inner spacers (see paragraph 0082 and 00146)
Regarding Claim 2, for forming a semiconductor device structure as claimed in claim 1, wherein the dielectric nanostructures comprise silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or a combination thereof (see paragraphs 0057, 0058, 0062, 0063)
Regarding Claim 3, wherein the formation of the dielectric nanostructures comprises filling two or more dummy material layers, and the two or more dummy material layers are made of a same material (see paragraphs 0060, 0099)
Regarding Claim 4, wherein the formation of the dielectric nanostructures comprises filling two or more dummy material layers, and some of the two or more dummy material layers are made of different materials (see paragraphs 0060, 0099)
Regarding Claim 5, partially removing the dielectric nanostructures to pull back the side edges of the dielectric nanostructures before the inner spacers 132 are formed.
Regarding Claim 6, removing the dielectric nanostructures after the inner spacers 132 are formed; and forming a metal gate stack wrapped around the semiconductor nanostructures.
Regarding Claim 7, the dielectric nanostructures (for example element 134) are removed using an etching process, the inner spacers 132 have a first sub-layer and a second sub-layer, the second sub-layer is between the epitaxial structure and the first sub-layer, and the first sub-layer has a higher etching resistance to the etching process than the second sub-layer.
Regarding Claim 8, wherein each of the semiconductor nanostructures has a line width roughness in a range from about 0 nm to about 0.9 nm.
Regarding Claim 9, wherein each of the semiconductor nanostructures has a sheet rounding in a range from about 0 nm to about 1.9 nm.
Regarding Claim 10, wherein the dielectric nanostructures and the inner spacers 132 are made of different dielectric materials.
Regarding Claim 11, in paragraphs 0023, 09024, 0025, 0026, 0027, 0047, 0048, 0049 (and especially paragraph 0049), 0050, 0087 and 0088, Ko et al. discloses a method for forming a semiconductor device structure, comprising: forming a plurality of semiconductor layers and a plurality of sacrificial layers over a substrate, wherein the semiconductor layers and the sacrificial layers are laid out in an alternating manner; forming a dummy gate stack partially covering the semiconductor layers and the sacrificial layers; partially removing the semiconductor layers and the sacrificial layers to form a recess exposing side edges of the semiconductor layers and the sacrificial layers after the dummy gate stack is formed; replacing the sacrificial layers with a plurality of dielectric nanostructures after the recess is formed, wherein remaining portions of the semiconductor layers form a plurality of semiconductor nanostructures; forming an epitaxial structure on side edges of the semiconductor nanostructures; removing the dummy gate stack and the dielectric nanostructures; and forming a metal gate stack 172 wrapped around the semiconductor nanostructures (see paragraph 0123)
Regarding Claim 12, removing the sacrificial layers to form a plurality of second recesses; forming a dielectric layer overfilling the second recesses; and partially removing the dielectric layer, wherein remaining portions of the dielectric layer form the dielectric nanostructures in the second recesses (see paragraph 0061 and 0073)
Regarding Claim 13, the formation of the dielectric layer comprises: forming a first sub-layer of the dielectric layer to partially fill the second recesses; and forming a second sub-layer of the dielectric layer to fill remaining space of the second recesses (see paragraph 0061, 0073)
Regarding Claim 14, the first sub-layer is formed using a first deposition process, the second sub-layer is formed using a second deposition process, and the second deposition process has a better gap-filling ability than the first deposition process (see paragraphs 0021, 0123 and 0146)
Regarding Claim 15, in paragraphs 0023, 09024, 0025, 0026, 0027, 0047, 0048, 0049 (and especially paragraph 0049), 0050, 0087 and 0088, Ko et al. discloses a semiconductor device structure, comprising: a plurality of semiconductor nanostructures; a gate stack wrapped around the semiconductor nanostructures, wherein the semiconductor nanostructures have a line width roughness in a range from about 0 nm to about 0.9 nm; and a first epitaxial structure and a second epitaxial structure, wherein the semiconductor nanostructures are sandwiched between the first epitaxial structure and the second epitaxial structure.
Regarding Claim 16, the semiconductor nanostructures have a sheet rounding in a range from about 0 nm to about 1.9 nm.
Regarding Claim 17, a first chip-containing structure, wherein the semiconductor nanostructures, the first epitaxial structure, and the second epitaxial structure are within the first chip-containing structure; a plurality of second semiconductor nanostructures; a third epitaxial structure and a fourth epitaxial structure, wherein the second semiconductor nanostructures are sandwiched between the third epitaxial structure and the fourth epitaxial structure; and a second chip-containing structure bonded to the first chip-containing structure through dielectric-to-dielectric bonding and metal-to-metal bonding, wherein the second semiconductor nanostructures, the third epitaxial structure, and the fourth epitaxial structure are within the second chip-containing structure.
Regarding Claim 18, the second semiconductor nanostructures have a second line width roughness greater than the line width roughness of the semiconductor nanostructures (see paragraph 0021)
Regarding Claim 19, the second semiconductor nanostructures have a second sheet rounding greater than the sheet rounding of the semiconductor nanostructures (see paragraph 0025)
Regarding Claim 20, wherein the second semiconductor nanostructures have a higher atomic concentration of germanium impurities than that of the semiconductor nanostructures (see paragraph 0024)
Examiner is including Yu et al. (20220384605) as a pertinent prior art that is NOT relied upon that teaches the GAA device with inner spacers to reduce the parasitic capacitance and hence increase operation speed.
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 9/13/2026
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