Prosecution Insights
Last updated: October 04, 2026
Application No. 18/890,105

SENSOR PACKAGE STRUCTURE

Non-Final OA §103
Filed
Sep 19, 2024
Priority
Jun 05, 2024 — TW 113120761
Examiner
PARTHASARATHY, ROHIT
Art Unit
Tech Center
Assignee
Tong Hsing Electronic Industries Ltd.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
43 granted / 48 resolved
+29.6% vs TC avg
Moderate +14% lift
Without
With
+13.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
25 currently pending
Career history
65
Total Applications
across all art units

Statute-Specific Performance

§103
59.1%
+19.1% vs TC avg
§102
19.8%
-20.2% vs TC avg
§112
18.6%
-21.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 48 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1,4, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over US10475937B1 (Jones) in view of US20210288190A1 (Liu). Regarding Claim 1, Jones discloses a sensor package structure (Fig. 2A or 4A, el. 100, Para. 7, ll. 8-9), comprising: a substrate (Fig. 2A or 4A, el. 102, Para. 7, ll. 9-10); a light-sensing chip (Fig. 2A or 4A, el. 104, Para. 6, ll. 63-66) and a light emitting chip (Fig. 2A or 4A, el. 108, Para. 6, ll. 63-66) disposed on and electrically coupled to the substrate (Fig. 2A or 4A, Para. 6, ll. 63-66), wherein a top surface of the sensor chip includes a sensing region (Para. 8, ll. 9-12); a light-permeable layer (Fig. 2A or 4A, el. 112, Para. 7, ll. 35-38) having an inner surface (Fig. 4A, el. 111, Para. 11, ll. 13-16), an outer surface (Fig. 2A, el. 113, Para. 9, ll. 16-20), and a surrounding lateral surface that is connected to the inner surface and the outer surface (Fig. 2A or 4A, where the lateral surface is the side surface of el. 112); a light block barrier (Fig. 2A or 4A, el. 110, Para. 8, ll. 4-5) having a top side that is fixed onto the inner surface of the light-permeable layer (Fig. 2A or 4A), wherein the light block barrier is arranged between the light-sensing chip and the light emitting chip (Co. 7, ll. 20-25). Jones further discloses that the package may include multiple sensor dies (Col. 8, ll. 5-7). Jones does not disclose two sensor chips disposed on a substrate, each of which having a carrying region that surrounds a sensing region; two ringed-shaped supporting layers respectively disposed on the carrying region of the two sensor chips and respectively surrounding the sensing regions of the two sensor chips. Jones does not disclose that the inner surface of the light-permeable layer is dispose on top sides of two ring-shipped supporting layers, and each of the two ring-shaped supporting layers, the light-permeable layer, and the top surface of a corresponding one of the two sensor chips jointly define an enclosed space. Jones also does not disclose an encapsulant formed on the substrate, wherein the two sensor chips, the two ring-shaped supporting layers, the light block barrier, and the light-permeable layer are embedded in the encapsulant, and the outer surface of the light-permeable layer is at least partially exposed from the encapsulant. Liu discloses a sensor package (Figs. 1-5, el. 100, Para. [0017]) comprising a substrate (Fig 1, el. 100, Para. [0017]), a sensor chip (Fig. 1, el. 2Para. [0017]) wherein a top surface of the sensor chip includes a sensing region (Fig. 5, el. 21, Para. [0021]) and a carrying region (Fig. 5, el. 22, Para. [0021] that surrounds the sensing region (Para. [0021]); a ring-shaped supporting layer (Fig. 2, el. 4, Para. [0023]) disposed on the carrying region of the sensor chip and surrounding the sensor region of the sensor chip (Para. [0024]); a light-permeable layer (Fig. 2, el. 5, Para. [0027]) having an inner surface (Fig. 2, el. 52, Para. [0027]), an outer surface (Fig. 2, el. 51, Para. [0027]), and a surrounding lateral surface (Fig. 2, el. 53, Para. 0027] that is connected to the inner surface and the outer surface (Para. [0027]), wherein the inner surface of the light-permeable layer is disposed on top sides of the ring-shaped supporting layer (Para. [0027]), and the ring-shaped supporting layer, the light-permeable layer and top surface of the sensor chip define an enclosed space (Para. [0027]); and an encapsulant formed on the substrate (Para. [0029]) wherein the sensor chip, ring supporting layer, and light-permeable layer are embedded in the encapsulant, and the outer surface of the light-permeable layer is at least partially exposed from the encapsulant (Para. [0028]). First, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to replace the light-emitting chip of Jones with another sensor chip. Jones already contemplates using multiple sensor chips in the package, and a person of ordinary skill in the art would see that the second sensor can replace the light-source (note that Jones also teaches that the package need not include any light source – Col. 8, ll. 35-38). Second, it would have been obvious to a person of ordinary skill in the art to use the ring layer of Liu in the package of Jones, including having an enclosed space defined by the top of a sensor chip, the side walls of the ring layer, and the bottom surface of the light permeable surface. As disclosed by Liu, this configuration has the benefit of allowing light to scatter, thereby reducing glare (Para. [0008]). Regarding Claim 4, Jones in view of Liu discloses the sensor package structure according to claim 1, wherein the light block barrier has two lateral surfaces that respectively face toward the two ring-shaped supporting layers and that are embedded in the encapsulant (this will come about when Jones is modified by Liu -see claim 1) Regarding Claim 10, Jones in view of Liu discloses the sensor package structure according to claim 1, wherein a sum of heights of any one of the two ring-shaped supporting layers and a corresponding one of the two sensor chips is equal to a sum of heights of another one of the two ring-shaped supporting layers and a corresponding one of the two sensor chips (this will occur when Jones is modified by Liu by adding the ring-shaped structures to the two sensors of Jones). Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of Liu. Regarding Claims 7 and 8, Jones in view of Liu discloses the sensor package structure according to claim 1. Liu further discloses a sensor package comprising a plurality of metal wires each having a first end and a second end, the first ends are connected to the substrate, and the second ends are connected to the top surface of the sensor chip (Para. [0019-23]), and that the metal wires are embedded in the encapsulant (Para. [0028]). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add the metal wires disclosed by Liu to the package of Jones in view of Liu. As disclosed by Liu, the addition of the metal wires allows the substrate to be electrically coupled to the sensor chip (Para. [0022]). Further, it would have been obvious to cover the metal wires with the encapsulant. This has the well-known benefit of protecting the wires from the environment. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of US20180376041A1 (Miura). Regarding Claim 11, Jones discloses a sensor package structure (Fig. 2A or 4A, el. 100, Para. 7, ll. 8-9), comprising: a substrate (Fig. 2A or 4A, el. 102, Para. 7, ll. 9-10); a frame (Fig. 2A, el. 106, Col. 7, ll. 10-13) formed on the substrate to jointly define a chip receiving slot (Col. 7, ll. 16-20), a light-sensing chip (Fig. 2A or 4A, el. 104, Para. 6, ll. 63-66) and a light emitting chip (Fig. 2A or 4A, el. 108, Para. 6, ll. 63-66) disposed on and electrically coupled to the substrate (Fig. 2A or 4A, Para. 6, ll. 63-66), wherein the two chips are arranged in the chip receiving slot (Fig. 2A, Col. 7, ll. 20-23); a light-permeable layer (Fig. 2A or 4A, el. 112, Para. 7, ll. 35-38) having an inner surface (Fig. 4A, el. 111, Para. 11, ll. 13-16), an outer surface (Fig. 2A, el. 113, Para. 9, ll. 16-20), and a surrounding lateral surface that is connected to the inner surface and the outer surface (Fig. 2A or 4A, where the lateral surface is the side surface of el. 112, wherein the inner surface of the light-permeable layer is disposed on the frame so as to enclose the chip receiving slod and an inner space of the chip receiving slot (Fig. 2A, Col. 7, ll. 47-50); and a light block barrier (Fig. 2A or 4A, el. 110, Para. 8, ll. 4-5) having a top side that is fixed onto the inner surface of the light-permeable layer (Fig. 2A or 4A), wherein the light block barrier is arranged between the light-sensing chip and the light emitting chip (Co. 7, ll. 20-25). Jones does not disclose that the frame is ring-shaped. Miura discloses a sensor package structure (Figs. 1A-B, el. 21, Para. [0015]) comprising a ring-shaped frame (Figs. 1A-B, el. 2, Para. [0016]) surrounding a sensor (Fig. 1A). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to use the ring-shaped frame of Miura in the package of Jones. Using the ring-shaped frame has the benefit of providing more stability to uphold the light permeable layer. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of Miura and Liu. Regarding Claim 17, Jones in view of Miura discloses the sensor package structure according to Claim 11. Jones in view of Muira does not disclose a plurality of metal wires each having a first end and a second end, wherein the metal wires are not in contact with the light block barrier and the ring-shaped frame, the first ends of the metal wires are connected to the substrate, and the second ends of the metal wires are connected to the top surfaces of the two sensor chips Liu discloses a sensor package comprising a plurality of metal wires each having a first end and a second end, the first ends are connected to the substrate, and the second ends are connected to the top surface of the sensor chip (Para. [0019-23]), and that the metal wires are embedded in the encapsulant (Para. [0028]). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add the metal wires disclosed by Liu to the package of Jones in view of Liu. As disclosed by Liu, the addition of the metal wires allows the substrate to be electrically coupled to the sensor chip (Para. [0022]). Allowable Subject Matter Claims 2-3, 5-6, 9, 12-16, and 18-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claims 2-3, none of the prior art of record teaches, suggests or renders obvious, either alone or in combination wherein a bottom side of the light block barrier is not fixed to the substrate. Regarding Claim 5, none of the prior art of record teaches, suggests or renders obvious, either alone or in combination wherein the light block barrier has two roughened lateral surfaces that respectively face toward the two ring-shaped supporting layers. Regarding Claim 6, none of the prior art of record teaches, suggests or renders obvious, either alone or in combination wherein the light block barrier has two end sides are flush with the surrounding lateral surface of the light permeable layer. Regarding Claim 9, none of the prior art of record teaches, suggests or renders obvious, either alone or in combination wherein at least one of the metal wires is embedded in the encapsulant and one of the two ring-shaped supporting layers. Regarding Claims 12-13, none of the prior art of record teaches, suggests or renders obvious, either alone or in combination wherein a bottom side of the light block barrier is not fixed to the substrate. Regarding Claim 14, none of the prior art of record teaches, suggests or renders obvious, either alone or in combination wherein the light block barrier has two roughened lateral surfaces that respectively face toward the two ring-shaped supporting layers. Regarding Claims 15-16 none of the prior art of record teaches, suggests or renders obvious, either alone or in combination wherein the light block barrier has two end sides are flush with the surrounding lateral surface of the light permeable layer. Regarding Claims 18-20 none of the prior art of record teaches, suggests or renders obvious, either alone or in combination wherein the ring-shaped frame has a ring-shaped notch recessed in an inner side thereof. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Sep 19, 2024
Application Filed
Sep 21, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12730135
Chip Package with Contact Clip
3y 11m to grant Granted Sep 08, 2026
Patent 12733543
Power Semiconductor Module and Manufacturing Method
3y 7m to grant Granted Sep 08, 2026
Patent 12727462
CONTACT STRUCTURE, SEMICONDUCTOR DEVICE COMPRISING THE SAME, AND METHOD FOR FABRICATING THE SAME
2y 11m to grant Granted Sep 01, 2026
Patent 12721187
SEMICONDUCTOR DEVICE
3y 1m to grant Granted Aug 25, 2026
Patent 12713923
SEMICONDUCTOR DEVICE MODULE AND METHOD FOR MANUFACTURING SAME
3y 8m to grant Granted Aug 18, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+13.9%)
3y 2m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 48 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month