DETAILED ACTION
Examiner’s Note
The prior arts cited in PTO-892 but not used in the current rejection are related to the claimed novelty and can also be used to reject the claims 1-20. Applicant is requested to review those prior arts to overcome the future rejection using these arts.
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 9 and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sutardja (US 20070034903 A1, hereinafter Sutardja’903).
Regarding independent claim 1, Sutardja’903 teaches, “A curved-gate transistor structure (fig. 1-16; ¶ [0001] - ¶ [0120]), comprising M*N semiconductor structural units (fig. 11) arranged in an M*N array, wherein M and N are both positive integers;
wherein each of the semiconductor structural units comprises a gate region (200), a source region (224), and a drain region (220),
wherein the source region (224) is located on a first side of the gate region (200), and the drain region (220) is located on a second side of the gate region (200);
wherein the gate region (200) of each semiconductor structural unit is curved, wherein each of the semiconductor structural units comprises a convex unit (210) surrounded by the gate region (200) of the semiconductor structural unit, and the convex unit has a convex shape; and
wherein each semiconductor structural unit further comprises body contact regions (260), the body contact regions are connected with a well region (N-Well) or a substrate where the source region (224) and the drain region (220) of the corresponding semiconductor structural unit are located, and wherein the body contact regions (260) and the source region (224) are both on the first side of the gate region (200)”.
Regarding claim 2, Sutardja’903 further teaches, “The curved-gate transistor structure according to claim 1, wherein the gate region (200, fig. 11) of each semiconductor structural unit comprises two curved branches, and the two branches are separated from each other and located above an active region where the semiconductor structural unit is located; wherein each of the branches of the gate region is symmetric with respect to a first straight line, and the two branches are symmetric with respect to a second straight line; wherein the first straight line and the second straight line both pass through a center of the semiconductor structural unit and are perpendicular to each other; and wherein when N>1, branches of the gate regions of each two adjacent semiconductor structural units in the same row are correspondingly connected with each other”.
Regarding claim 3, Sutardja’903 further teaches, “The curved-gate transistor structure according to claim 1, wherein in each semiconductor structural unit, either the source region (224, fig. 11) or the drain region (220) is located within the convex unit (210)”.
Regarding claim 4, Sutardja’903 further teaches, “The curved-gate transistor structure according to claim 2, wherein each of the branches of the gate region (200, fig. 11) of each semiconductor structural unit comprises multiple straight segments, and wherein angles between adjacent straight segments are obtuse angles”.
Regarding claim 5, Sutardja’903 further teaches, “The curved-gate transistor structure according to claim 4, wherein junctions (fig. 8-9) between the adjacent straight segments of each of the branches are arced”.
Regarding claim 6, Sutardja’903 further teaches, “The curved-gate transistor structure according to claim 1, wherein each semiconductor structural unit further comprises one or more drain contact regions and one or more source contact regions; wherein the drain contact regions are located on the drain region, and wherein the source contact regions are located on the source region (see figs. 6-12, source contact regions 70, drain contact regions 334)”.
Regarding claim 7, Sutardja’903 further teaches, “The curved-gate transistor structure according to claim 2, wherein each branch of the gate region (200, fig. 11) of each semiconductor structural unit comprises 4k+1 straight segments, wherein a first straight segment, a 2k+1th straight segment and a 4k+1th straight segment of each branch are parallel to each other, and wherein k is a positive integer”.
Regarding claim 9, Sutardja’903 further teaches, “The curved-gate transistor structure according to claim 7, wherein when M>1, contact regions are provided between 2k+1th straight segments of two adjacent branches of two adjacent semiconductor structural units located in the same column (fig. 11, Sutardja’903)”.
Regarding claim 18, Sutardja’903 further teaches, “The curved-gate transistor structure according to claim 1, wherein contact regions within each convex unit (210, fig. 11) comprises the body contact regions and the source contact regions (260) and exhibit axial and central symmetry in their arrangement, and wherein each row of the contact regions are either all body contact regions or all source contact regions”.
Regarding claim 20, Sutardja’903 further teaches, “The curved-gate transistor structure according to claim 18, wherein a quantity of contact regions (see annotated fig. 11 below) in a first row within each convex unit is the same as that of a last row, and less than that of each intermediate row.
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Sutardja’903 as applied to claim 7 above, and further in view of Ma et al. (CN 111446236 A, hereinafter Ma’236).
Regarding claim 8, Sutardja’903 teaches all the limitations described in claim 7.
But Sutardja’903 is silent upon the provision of wherein in each semiconductor structural unit, contact regions are provided between first straight segments of the two branches of the gate region, and between 4k+1th straight segments of the two branches of the gate region.
However, Ma’236 teaches a similar device (fig. 5-6), wherein in each semiconductor structural unit, contact regions a(320a) re provided between first straight segments of the two branches of the gate region, and between 4k+1th straight segments of the two branches of the gate region.
Sutardja’903 and Ma’236 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Sutardja’903 with the features of Ma’236 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Sutardja’903 and Ma’236 to place the contact regions according to the teachings of Ma’236 with a motivation as Ma’236 in their abstract, ‘The invention improves the shape consistency of the gate pattern, and reduces the total area of the gate pattern and the area of the single gate pattern, so as to improve the parasitic load uniformity of the gate layer, reduce the parasitic load, so as to reduce the whole layout size of the memory, and improve the performance of the formed memory’.
Claims 10-17 are rejected under 35 U.S.C. 103 as being unpatentable over Sutardja’903 as applied to claim 2 above, and further in view of Freidoon (EP 0766316 A1, hereinafter Freidoon’316).
Regarding claim 10, Sutardja’903 teaches all the limitations described in claim 2.
Sutardja’903 further teaches, wherein each semiconductor structural unit further comprises source contact regions and the body contact regions in a line and drain regions in a line (see fig. 11, 8-9 etc.) and these two regions are alternating in a width direction of the semiconductor structural unit.
But Sutardja’903 may not be explicit upon the provision of wherein these source contact regions and the body contact regions in a line and drain regions are connected to metal blocks/line.
However, contacts for S/D and body regions are created to connect these regions to I/O, power supplies and to other elements in the circuit using metal line/layer. Example prior art Freidoon’316 shows a similar curved-gate transistor structure (fig. 2), wherein each semiconductor structural unit further comprises first metal blocks (17a) and second metal blocks (18), wherein the second metal blocks (18) are connected to the drain contact regions (DC), and wherein the first metal blocks (17a) are connected to the source contact regions (SC) and the body contact regions (Sutardja’903 teaches source and body contact regions are shorted in fig. 6-7); wherein the first metal blocks and the second metal blocks (17a, 18, fig. 2, Freidoon’316) are parallel and alternating in a width direction of the semiconductor structural unit.
Sutardja’903 and Freidoon’316 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Sutardja’903 with the features of Freidoon’316 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Sutardja’903 and Freidoon’316 to include metal blocks according to the teachings of Freidoon’316 as this is conventional and essential elements of a semiconductor device.
Note: claim 10 can also be rejected using prior art Lee (US 20070096187 A1, fig. 1A etc.).
Regarding claim 11, Sutardja’903 modified with Freidoon’316 further teaches, “The curved-gate transistor structure according to claim 10, wherein the first metal blocks (17a, fig. 2, Freidoon’316) and the second metal blocks (18) are parallel and alternating along a first direction, wherein the first metal blocks and the second metal blocks have equal lengths along a second direction, wherein the first direction is parallel to the first straight segment of each branch of the gate region (ST) in each semiconductor structural unit, and wherein the second direction is perpendicular to the first direction”.
Regarding claim 12, Sutardja’903 modified with Freidoon’316 further teaches, “The curved-gate transistor structure according to claim 10, wherein the first metal blocks (17a, fig. 2, Freidoon’316) and the second metal blocks (18) are parallel and alternating along a second body direction, wherein the first metal blocks and the second metal blocks have equal lengths along a first direction, wherein the first direction is parallel to the first straight segments of each branch of the gate region in each semiconductor structural unit, and wherein the second direction is perpendicular to the first direction”.
Regarding claim 13, Sutardja’903 modified with Freidoon’316 further teaches, “The 13. The curved-gate transistor structure according to claim 10, wherein when M>1, all branches of the gate regions (12, 13) of the curved-gate transistor structure are connected to a same potential through a fifth metal block”. Regarding, ‘same potential’, describe an intended manner in which the claimed device to be employed. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP § 2144.02.
Regarding claims 14-15, Sutardja’903 modified with Freidoon’316 further teaches gate regions of the semiconductor structural units located in different rows (fig. 11). But Sutardja’903 modified with Freidoon’316 may not be explicit upon the potentials applied to the gates. However, these limitations describe an intended manner in which the claimed device to be employed. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP § 2144.02.
Regarding claims 16-17, Sutardja’903 modified with Freidoon’316 further teaches first metal blocks. But Sutardja’903 modified with Freidoon’316 may not be explicit upon the potentials applied to the first metal blocks. However, these limitations describe an intended manner in which the claimed device to be employed. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP § 2144.02.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Sutardja’903 as applied to claim 18 above, and further in view of Kuwazawa (US 20150035056 A1).
Regarding claim 19, Sutardja’903 teaches all the limitations described in claim 18.
But Sutardja’903 is silent upon the provision of wherein the source contact regions and the body contact regions are alternately arranged in one column.
However, Kuwazawa teaches a semiconductor device, wherein the source contact regions (125a, fig. 3) and the body contact regions (125b) are alternately arranged in one column.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Sutardja’903 and Kuwazawa to arrange the source contact regions and body contact regions alternately according to the teachings of Kuwazawa with a motivation of reducing contact resistance as Kuwazawa described in ¶ [0008].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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