Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “an encapsulant” of claim 2 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claim(s) 1-4,7-10 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by US 20240404926 A1 (Chi).
Regarding claim 1, Chi shows (Fig. 1) an electronic package (100, para 29) comprising:
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a plurality of signal pins (170, para 31);
a substrate (112, para 30) electrically connected to each pin of the plurality of signal pins;
a base (140, board, para 32) comprising a plurality of apertures (162+144, para 31), wherein each respective pin of the plurality of signal pins extends through a respective aperture of the plurality of apertures; and
a plurality of seals (144, para 32), wherein a respective seal of the plurality of seals is disposed in each respective aperture (Fig. 1B) of the plurality of apertures and contacts a peripheral region of each respective signal pin of the plurality of signal pins.
Regarding claim 2, Chi shows (Fig. 1) further comprising an encapsulant (150, para 29) at least partially encapsulating at least a portion of the base (140) and at least a portion of each signal pin (170, bottom portion 172) of the plurality of signal pins.
Regarding claim 3, Chi shows (Fig. 1) wherein the respective seal of the plurality of seals further contacts a wall (vertical portion of 140 contacting the seals) of each respective aperture.
Regarding claim 4, Chi shows (Fig. 1) wherein each signal pin of the plurality of signal pins (170) includes a base region (shown above) and a shoulder region (shown above) and, wherein the base region has a first cross-sectional area and the shoulder region has a second cross-sectional area, and wherein the first cross-sectional area is less than the second cross-sectional area (as shown).
Regarding claim 7, Chi shows (Fig. 1) wherein each signal pin (170) of the plurality of signal pins is configured to be electrically coupled to a signal board (140, board, para 32) and to conduct power or signals to or from the electronic package (through 116 and 130).
Regarding claim 8, Chi shows (Fig. 1) wherein each signal pin (170) is configured to be electrically coupled to the signal board by press fit (para 31), soldering, or with conductive glue.
Regarding claim 9, Chi shows (Fig. 1), wherein each signal pin (170) comprises an enlarged region (shoulder region as shown above) configured to limit a length of each pin that protrudes beyond the signal board.
Regarding claim 10, Chi shows (Fig. 1) wherein each signal pin (170) of the plurality of signal pins is configured to be electrically connected to the substrate by press fit (para 31), soldering, brazing, or swaging.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chi as applied to claim 1 above, further in view of US 20230170269 A1 (Wu).
Regarding claim 5, Chi shows seal that is laminated within a bottom of the respective aperture.
Chi does not show wherein each respective seal comprises a flexible layer that is laminated within a bottom of the respective aperture.
Wu shows (Fig. 6) wherein each respective seal (60) comprises a flexible layer (rubber, para 53) that is laminated within a bottom of the respective aperture (aperture for pins 50 through board 70).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to modify the invention of Chi, including seal, with the invention of Wu.
The motivation to do so is that the combination produces a certain degree of freedom by the flexibility of movement for the pins.
Regarding claim 6, Chi as previously modified with Wu shows wherein the flexible layer comprises silicone, silicone rubber (Wu, para 53), or elastomer.
2. Claim(s) 11,13-15,18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chi in view of US 20150287665 A1 (Hanada).
Regarding claim 11, Chi shows (Fig. 1) an integrated power system comprising:
electronic package (100) comprising:
a plurality of signal pins (170);
a substrate (112) electrically connected to each pin of the plurality of signal pins;
a base (140) comprising a plurality of apertures (162+144), wherein each respective pin of the plurality of signal pins extends through a respective aperture of the plurality of apertures; and
a plurality of seals (144), wherein a respective seal of the plurality of seals is disposed in each respective aperture of the plurality of apertures and contacts a peripheral region of each respective signal pin of the plurality of signal pins.
Chi does not show a plurality of electronic packages.
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Hanada shows (Fig. 27-28) a plurality of electronic packages (Q1-Q6, para 183).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Hanada, with plurality of electronic packages, to the invention of Chi.
The motivation to do so is that the combination produces the predictable result of multiple devices required by the power system.
Regarding claim 18, Chi in view of Hanada shows a signal board (140, board, para 32, Chi) and wherein each signal pin (170, Chi) of the plurality of signal pins is configured to be electrically coupled to the signal board.
Regarding claims 13-15 and 19-20, the prior art as noted in the above rejection of claims 2-4 and 8,10 respectively, discloses the entire claimed invention.
3. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chi in view of Hanada as applied to claim 11 above further in view of US 20230223314 A1 (Yoshida).
Regarding claim 12, Chi in view of Hanada shows electronic package.
Chi in view of Hanada does not show a common heatsink and wherein each electronic package of the plurality of electronic packages is in contact with the common heatsink.
Yoshida shows (Fig. 4) a common heatsink (10, para 31) and wherein each electronic package (2, para 32) of the plurality of electronic packages is in contact with the common heatsink.
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Yoshida, with common heatsink, to the invention of Chi in view of Hanada.
The motivation to do so is that the combination produces the predictable result of suitable cooling for the packages.
4. Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chi in view of Hanada as applied to claim 11 above further in view of Wu.
Regarding claims 16-17, the prior art as noted in the above rejection of claims 5-6 respectively, discloses the entire claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WASIUL HAIDER whose telephone number is (571)272-1554. The examiner can normally be reached M-F 9 a.m. - 6 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WASIUL HAIDER/Primary Examiner, Art Unit 2812
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