DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 08/28/2026 Amendment.
Claims 1-16 are pending and examined. Claims 11-16 are newly added.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-11 of U.S. Patent No. 12,106,823. Although the claims at issue are not identical, they are not patentably distinct from each other because both recite limitations of a semiconductor device comprising a source follower circuit and a bootstrap circuit, wherein the source follower circuit is configured to increase the output signal to a second potential higher than the first potential at a second state, and wherein the bootstrap circuit is configured to increase the input signal along the increase of the output signal.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-11, 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 7,545,357 to Miyazawa et al. (hereafter Miyazawa) OR US 11,276,711 to Inoue et al. (hereafter Inoue).
With Miyazawa reference:
Regarding independent claim 1, Miyazawa teaches a semiconductor device comprising a holding circuit (FIG. 11C: comprising transistor N1 and capacitor CB), a source follower circuit (FIG. 11C: transistor NMOS3) and a bootstrap circuit (FIG. 11C: comprising capacitor CB and transistor NMOS3),
wherein the bootstrap circuit is configured to input an input signal held by the holding circuit to the source follower circuit (FIG. 11C: input signal VIN held by capacitor CB and provided to the gate of transistor NMOS3),
wherein the input signal is analog data (FIG. 11B: input signal VIN is seen analog value as shown),
wherein the source follower circuit is configured to output a first potential as an output signal at a first state (FIGS. 11B and 11C: node N2 is at VSS when input VIN is at VSS),
wherein the source follower circuit is configured to increase the output signal to a second potential higher than the first potential at a second state (FIGS. 11B and 11C: node N2 is at VN2 when input VIN is at VIN, wherein VN2>VIN), and
wherein the bootstrap circuit is configured to increase the input signal along the increase of the output signal (FIG. 11B: node N1 is increasing to VN1 along with VN2).
Regarding dependent claim 2, Miyazawa teaches wherein the first potential is a ground potential or a low power supply potential (FIGS. 11B and 11C: node N2 is at VSS when input VIN is at VSS).
Regarding dependent claim 3, Miyazawa further teaches an output terminal (FIG. 11C: i.e. node N2), wherein the source follower circuit is configured to output the output signal to the output terminal, wherein the source follower circuit comprises a transistor (FIG. 11C: transistor NMOS3), wherein the bootstrap circuit comprises the transistor and a capacitor (FIG. 11C: capacitor CB and transistor NMOS3), wherein one electrode of the capacitor is electrically connected to the gate of the transistor, wherein the other electrode of the capacitor is electrically connected to the output terminal, and wherein one of a source and a drain of the transistor is electrically connected to the output terminal (see FIG. 11C).
Regarding dependent claim 4, Miyazawa teaches wherein the transistor is in an off state at the first state (FIG. 11B: i.e. when VIN is at VSS, NMOS3 is turned off and at VSS), and wherein the transistor is in an on state at the second state (FIG. 11B: i.e. when VIN is at VIN, NMOS3 is turned on and at VN2).
Regarding dependent claim 5, Miyazawa teaches wherein the transistor comprises an oxide semiconductor in a semiconductor layer where a channel is formed (NMOS3 implying such).
Regarding dependent claim 12, Miyazawa teaches wherein the second transistor comprises an oxide semiconductor in a semiconductor layer where a channel is formed (FIG. 11C: the transistors are MOS transistors).
With Inoue reference:
Regarding independent claim 1, Inoue teaches a semiconductor device comprising a holding circuit (FIG. 1A: comprising transistor M1 and capacitor MCU) a source follower circuit (FIG. 1A: transistor M3) and a bootstrap circuit (FIG. 1A: comprising capacitor MCU and transistor M3),
wherein the bootstrap circuit is configured to input an input signal held by the holding circuit to the source follower circuit (FIG. 1A: input signal IN held by capacitor MCU, and provided to the gate of transistor M3),
wherein the input signal is analog data (FIG. 2: input signal IN is seen having analog value as shown)
wherein the source follower circuit is configured to output a first potential as an output signal at a first state (FIG. 2: node PREOUT is at VSS when input IN is at VSS during t0),
wherein the source follower circuit is configured to increase the output signal to a second potential higher than the first potential at a second state (FIG. 2: node PREOUT during t2-t3, wherein PREOUT>IN during t2-t3), and
wherein the bootstrap circuit is configured to increase the input signal along the increase of the output signal (FIG. 2: BOOT is increasing along with PREOUT during t2-t3).
Regarding dependent claim 2, Inoue teaches wherein the first potential is a ground potential or a low power supply potential (FIG. 2: node PREOUT is at VSS when input IN is at VSS during t0).
Regarding dependent claim 3, Inoue further teaches an output terminal (FIG. 1A: i.e. PREOUT), wherein the source follower circuit is configured to output the output signal to the output terminal, wherein the source follower circuit comprises a transistor (FIG. 1A: transistor M3), wherein the bootstrap circuit comprises the transistor and a capacitor (FIG. 1A: capacitor MCU and transistor M3), wherein one electrode of the capacitor is electrically connected to the gate of the transistor, wherein the other electrode of the capacitor is electrically connected to the output terminal, and wherein one of a source and a drain of the transistor is electrically connected to the output terminal (see FIG. 1A).
Regarding dependent claim 4, Inoue teaches wherein the transistor is in an off state at the first state (FIG. 1A: i.e. when IN is at VSS during t0, NMOS3 is turned off and at VSS during t0), and wherein the transistor is in an on state at the second state (FIG. 1A: i.e. when IN is at VDD of 5V, NMOS3 is turned on and at VDDH higher than VDD).
Regarding dependent claim 5, Inoue teaches wherein the transistor comprises an oxide semiconductor in a semiconductor layer where a channel is formed (see 8:40-47).
Regarding independent claim 6, Inoue teaches a semiconductor device comprising a first holding circuit (FIG. 1A: comprising transistor M1 and capacitor MCU), a second holding circuit (FIG. 1A: capacitor MCL), a source follower circuit (FIG. 1A: transistors M3 and M4), a first bootstrap circuit (FIG. 1A: comprising capacitor MCU and transistor M3) and a second bootstrap circuit (FIG. 1A: comprising capacitor MCL and transistor M4),
wherein the first bootstrap circuit is configured to input a first input signal held by the first holding circuit to the source follower circuit (FIG. 1A: first input signal IN held by capacitor MCU, and provided to the gate of transistor M3),
wherein the second bootstrap circuit is configured to input a second input signal held by the second holding circuit to the source follower circuit (FIG. 1A: second input signal INB held by capacitor MCL, and provided to the gate of transistor M4),
wherein the source follower circuit is configured to output a first potential as an output signal at a first state (FIG. 2: node PREOUT is at VSS when input IN is at VSS during t0),
wherein both of the first input signal and the second input signal are analog data (FIG. 2: input signals IN and INB are seen having analog values as shown),
wherein the source follower circuit is configured to increase the output signal to a second potential higher than the first potential at a second state (FIG. 2: node PREOUT during t2-t3, wherein PREOUT>IN during t2-t3),
wherein the second potential corresponds to a potential difference between the first input signal and the second input signal implicitly (because PREOUT is in response to both MCU and MCL),
wherein the first bootstrap circuit is configured to increase the first input signal along the increase of the output signal (FIG. 2: BOOT is increasing along with PREOUT during t2-t3), and
wherein the second bootstrap circuit is configured to increase the second input signal along the increase of the output signal (in similar way, gate voltage of M4 is increasing along with PREOUT during t2-t3).
Regarding dependent claim 7, Inoue teaches wherein the first potential is a ground potential or a low power supply potential (FIG. 2: node PREOUT is at VSS when input IN is at VSS during t0).
Regarding dependent claim 8, Inoue further teaches an output terminal (FIG. 1A: i.e. PREOUT), wherein the source follower circuit comprises a first transistor and a second transistor (FIG. 1A: transistor M3 and M4), wherein the first bootstrap circuit comprises the first transistor and a first capacitor (FIG. 1A: comprising capacitor MCU and transistor M3), wherein the second bootstrap circuit comprises the second transistor and a second capacitor (FIG. 1A: comprising capacitor MCL and transistor M4), wherein one electrode of the first capacitor is electrically connected to the gate of the first transistor (see FIG. 1A), wherein one electrode of the second capacitor is electrically connected to the gate of the second transistor (see FIG. 1A), wherein each of the other electrode of the first capacitor and the other electrode of the second capacitor is electrically connected to the output terminal (see FIG. 1A), wherein one of a source and a drain of the first transistor is electrically connected to the output terminal (see FIG. 1A), and wherein one of a source and a drain of the second transistor is electrically connected to the output terminal (see FIG. 1A).
Regarding dependent claim 9, Inoue implicitly teaches wherein both of the first transistor and the second transistor is in an off state at the first state, and wherein both of the first transistor and the second transistor is in an on state at the second state (because transistors M3 and M4 receive complementary signals in response to IN and INB).
Regarding dependent claim 10, Inoue teaches wherein each of the first transistor and the second transistor comprises an oxide semiconductor in a semiconductor layer where a channel is formed (see 8:40-47).
Regarding dependent claim 11, Inoue teaches wherein the holding circuit comprises a second transistor, wherein one of a source and a drain of the second transistor is connected to the one electrode of the capacitor (FIG. 1A: transistor M1), and wherein the second transistor is an off state at the first state (FIGS. 3A-3B: during t0, input IN is at 0V, output PREOUT is at 0V, and transistor M1 is in off state) and the second state (FIGS. 6A-6B: during t3, input IN is at a first high voltage, output PREOUT is at another high voltage, transistor M1 is also in off state).
Regarding dependent claim 13, Inoue teaches wherein the first holding circuit comprises a third transistor, wherein one of a source and a drain of the third transistor is connected to the one electrode of the first capacitor (FIG. 1A: transistor M1), and wherein the third transistor is an off state at the first state (FIGS. 3A-3B: during t0, input IN is at 0V, output PREOUT is at 0V, and transistor M1 is in off state) and the second state (FIGS. 6A-6B: during t3, input IN is at a first high voltage, output PREOUT is at another high voltage, transistor M1 is also in off state).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Inoue.
Regarding dependent claim 15, Inoue teaches wherein the second holding circuit comprises a transistor (FIG. 1A: transistor M2),
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that it would be functional equivalent to connect transistor M2 in the same manner as transistor M1 for input signal INB.
Claims 12, 14, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Inoue in view of Miyazawa.
Inoue teaches, as applied in prior rejection of claim 11, all claimed subject matter except further limitations set forth in the following claim(s).
Regarding dependent claim 12, Miyazawa teaches wherein the second transistor comprises an oxide semiconductor in a semiconductor layer where a channel is formed (FIG. 11C: the transistors are MOS transistors).
Since Inoue and Miyazawa are both from the same field of endeavor, the purpose disclosed by Miyazawa would have been recognized in the pertinent art of Inoue.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use MOS transistors because they are widely available in digital design.
Regarding dependent claims 14 and 16, see rejection applied to claim 12 above.
Response to Arguments
Applicant's arguments filed 08/28/2026 have been fully considered but they are not persuasive.
Applicant argues:
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In response to this argument, Examiner kindly directs the Applicant to a comparison between the circuitry shown in FIG. 1A of the pending application and that shown in FIG. 11C of Miyazawa. It appears that the two circuitries within the boxes are similar. There are no apparent reasons why the two circuitries with similar structures would operate differently.
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FIG. 1A of Present Invention vs. FIG. 11C of Miyazawa
With a similar approach, FIG. 1A of the pending application and that shown in FIG. 1A of Inoue are also similar, and they would also operate the same.
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FIG. 1A of Present Invention vs. FIG. 1A of Inoue
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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October 9, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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