CTNF 18/894,342 CTNF 88495 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1 – 20 are pending. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claim(s) 1 is/are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1 of copending Application No. 18/928,146 . Although the claims at issue are not identical, they are not patentably distinct from each other because they encompass substantially similar subject matter. This is a provisional nonstatutory double patenting rejection. The following table is presented for the purpose of a comparison of the conflicting claims between the applications. Application No. 18/894,342 Application No. 18/928,146 Claim 1 Claim 1 A test system for testing semiconductor package structures, comprising: a socket, comprising: a socket housing plate comprising a plurality of openings; and a plurality of contact pins extending through the openings into a housing of the socket; and a contact blade comprising a die pusher having a lower surface configured to contact an upper surface of a semiconductor package structure located in the socket, wherein the lower surface of the die pusher comprises a non-planar shape. A test system for testing semiconductor package structures, comprising: a socket, comprising: a socket housing plate comprising a plurality of openings in an upper surface of the socket housing plate, wherein the upper surface of the socket housing plate has a non-planar shape; and a plurality of contact pins extending through the openings into a housing of the socket; and a contact blade configured to contact an upper surface of a semiconductor package structure located in the socket. Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 10 – 20 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding Claim 10 , the prior art of record does not teach claimed limitation: “a lower surface configured to contact and apply pressure to a surface of a semiconductor package structure; and a trench in the lower surface of the die pusher” in combination with all other claimed limitations of claim 10 . Regarding Claims 11 – 16 , the claims are allowed as they further limit allowed claim 10. Regarding Claim 17 , the prior art of record does not teach claimed limitation: “providing a multi-chip module (MCM) package in a housing of a socket of a test system, wherein the MCM package comprises a first die and a second die mounted to a first side of a substrate and an encapsulant material located within a gap between the first die and the second die; and bringing a contact blade comprising a die pusher into contact with the MCM package such that bonding pads on a second side of the substrate contact corresponding contact pins within the housing of the socket” in combination with all other claimed limitations of claim 17 . Regarding Claims 18 – 20 , the claims are allowed as they further limit allowed claim 17. Comments The prior art of record found as a result of the search, does not teach alone or in combination all of the elements recited in claim(s) 1. Therefore, no prior art rejection for claim(s) 1 – 9 is presented in this action. However, Claim(s) 1 is/are provisionally rejected on the ground of nonstatutory double patenting. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : Wang et al. (US 2025/0369843 A1) disclose an upper press head for mechanical testing and electrical testing of a semiconductor chip package, comprising: a force receiving component configured to receive a downward force; a force delivering component, having an upper portion connected with the force receiving component and having a first lateral sectional area, and a lower portion having a second lateral sectional area less than the first lateral sectional area; a force applying component connected with the lower portion of the force delivering component and configured to apply the downward force to the semiconductor chip package, the force applying component comprising: a plurality of protrusions that are laterally separated from each other and are configured to simultaneously press the semiconductor chip package; and a space between two adjacent protrusions matches portions of solder balls of the semiconductor chip package (see claim 1). Han et al. (US 2024/0142493 A1) teach a socket for testing a semiconductor package, the socket comprising: a body having an internal space configured to accommodate a wafer level package; and a plurality of spacers on the body and positioned to contact a first surface of the wafer level package when the wafer level package is placed on the body, wherein the body includes a lower socket portion provided with through-holes, configured through which to receive meter reading pins that contact external connection terminals of the wafer level package, and an upper socket portion disposed above the lower socket portion, and wherein the plurality of spacers are disposed on a first surface of the lower socket portion that faces the first surface of the wafer level package when the wafer level package is placed on the body (see claim 1). Imaizumi et al. (US 2023/0105734 A1) suggest an electronic component testing apparatus that tests a DUT (device under test) disposed in a carrier, comprising: a test head comprising a socket; and an electronic component handling apparatus that presses the DUT in the carrier against the socket, wherein the socket comprises: contactors disposed to correspond to terminals of the DUT that are exposed to the socket via a first opening of the carrier; and a first wall projecting toward the carrier along a pressing direction of the DUT, and the electronic component handling apparatus aligns the terminals with the contactors by pressing the DUT against the socket such that a first pressing mechanism of the carrier presses the DUT against the first wall (see claim 1). Any inquiry concerning this communication or earlier communications from the examiner should be directed to GIOVANNI ASTACIO-OQUENDO whose telephone number is (571)270-5724. The examiner can normally be reached Monday - Friday, 8:00am - 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GIOVANNI ASTACIO-OQUENDO/Primary Examiner, Art Unit 2858 6/13/2026 Application/Control Number: 18/894,342 Page 2 Art Unit: 2858 Application/Control Number: 18/894,342 Page 3 Art Unit: 2858 Application/Control Number: 18/894,342 Page 4 Art Unit: 2858 Application/Control Number: 18/894,342 Page 5 Art Unit: 2858 Application/Control Number: 18/894,342 Page 6 Art Unit: 2858 Application/Control Number: 18/894,342 Page 7 Art Unit: 2858
Prosecution Insights