DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of claims 1-16 and the withdrawal of claims 17-20 in the reply filed on July 31, 2026 are acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4, 6-6 and 10 are rejected under 35 U.S.C. 103 as being obvious over Weber (US20060046516).
Regarding claim 1, Weber discloses a semiconductor processing method (abstract) comprising: providing an etchant precursor to a processing region of a semiconductor processing chamber, wherein a structure is disposed within the processing region, wherein the structure comprises a first silicon-containing material, and wherein the structure comprises a second silicon-containing material (the precursor used in the plasma etch process reads on an etchant precursor, paragraphs 0031-0032; layer 8 comprising organosilicate glass reads on a first silicon-containing material, layer 6 comprising silicon nitride reads on a second silicon-containing material, paragraph 0025); contacting the structure with the etchant precursor, wherein the contacting with the etchant precursor etches at least a portion of the second silicon-containing material (paragraphs 0031-0032); providing a carbon-containing precursor to a processing region of a semiconductor processing chamber (a precursor comprising -CH3 group reads on a carbon-containing precursor, paragraphs 0037-0038); and contacting the structure with the carbon-containing precursor, wherein the contacting with the carbon-containing precursor replenishes carbon in the first silicon-containing material (paragraph 0035 and claim 1). Weber is silent about the processing region for providing a carbon-containing precursor is the same as the processing region for providing an etchant precursor; however, there is no requirement in the entire disclosure of Weber to use two different processing chambers for the two processing steps. It is a common practice to use the same semiconductor processing chamber to perform different steps involving gas precursors.
Regarding claim 3, Weber discloses wherein the first silicon-containing material comprises a silicon-and-carbon-containing material (organosilicate glass reads on a silicon-and-carbon-containing material, paragraph 0025).
Regarding claim 5, the limitation recited in the “wherein” clause in the method claim simply expresses the intended result of the recited process; therefore, it is not accorded patentability weight. See MPEP 2111.04.
Regarding claim 6, Weber discloses wherein the carbon-containing precursor comprises hexamethyldisilazane (claim 16 and paragraph 0054).
Regarding claim 10, Weber discloses wherein a temperature in the semiconductor processing chamber is less than 500° C (paragraph 0039).Kim et al. (WO2004061994) as applied to claim 1 above.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Varadarajan et al. (US20110117678) in view of Naik et sl. (US20080102638).
Regarding claim 1, Varadarajan discloses a semiconductor processing method (abstract) comprising: providing an etchant precursor to a processing region of a semiconductor processing chamber, wherein a structure is disposed within the processing region, wherein the structure comprises a first silicon-containing material, and wherein the structure comprises a mask material (the precursor used in the plasma trench etch through mask 213 reads on an etchant precursor, paragraphs 0027 and 0068 and Fig. 2B; low-k dielectric layer 203 reads on a first silicon-containing material, paragraph 0027 and Fig. 2B); contacting the structure with the etchant precursor, wherein the contacting with the etchant precursor etches at least a portion of the mask material (paragraph 0068 and Fig. 2B); providing a carbon-containing precursor to a processing region of a semiconductor processing chamber (an alkyl silane reads on a carbon-containing precursor, paragraphs 0027 and 0040); and contacting the structure with the carbon-containing precursor, wherein the contacting with the carbon-containing precursor replenishes carbon in the first silicon-containing material (paragraph 0027 and 0071). Varadaranjan is silent about the processing region for providing a carbon-containing precursor is the same as the processing region for providing an etchant precursor; however, there is no requirement in the entire disclosure of Varadaranjan to use two different processing chambers for the two processing steps. It is a common practice to use the same semiconductor processing chamber to perform different steps involving gas precursors. Varadaranjan is silent about the mask being a second silicon-containing material. However, Varadaranjan discloses that the mask is used for plasma etching a dual damascene structure (paragraphs 0027 and 0068, Fig. 2B). In addition, Naik teaches that a silicon-containing material, such as silicon oxy-nitride, is used for etching a dual damascene structure (paragraph 0007). Therefore, it would have been obvious to one of ordinary skill, in the art before the effective filing date of the claimed invention, to use a known mask as taught by Naik, in the method of Varadaranjan for etching a damascene structure, with a reasonable expectation of success. It has been held that combining prior art elements according to known methods to yield predictable results is obvious. See MPEP 2143 I.(A).
Regarding claim 2, Naik discloses wherein the second silicon-containing material comprises a silicon-and-oxygen-containing material (silicon oxy-nitride, paragraph 0007).
Regarding claim 3, Varadaranjan discloses wherein the first silicon-containing material comprises a silicon-and-carbon-containing material (paragraph 0027).
Regarding claim 4, Naik discloses wherein the etchant precursor comprises a halogen-containing precursor (fluorocarbon gas, paragraph 0045).
Regarding claim 5, the limitation recited in the “wherein” clause in the method claim simply expresses the intended result of the recited process; therefore, it is not accorded patentability weight. See MPEP 2111.04.
Regarding claim 6, Varadaranjan discloses wherein the carbon-containing precursor comprises dimethyldichlorosilane (claim 23).
Regarding claim 7, Varadaranjan discloses exposing the structure to ultraviolet (UV) radiation while contacting the structure with the carbon-containing precursor (claim 1).
Regarding claim 8, Varadaranjan discloses wherein contacting the structure with the carbon-containing precursor and exposing the structure to ultraviolet (UV) radiation are performed simultaneously (claim 1).
Regarding claim 9, Varadaranjan discloses subsequent to contacting the structure with the carbon-containing precursor, providing a cleaning agent to the processing region of the semiconductor processing chamber; and contacting the structure with the cleaning agent, wherein the contacting with the cleaning agent removes a residue from the structure (hydrogen reads on a cleaning agent, paragraph 0072).
Regarding claim 10, Varadaranjan discloses wherein a temperature in the semiconductor processing chamber is less than 500° C (claim 19).
Allowable Subject Matter
Claims 11-16 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 11, the cited prior art of record, taken either alone or in combination, fails to disclose or render obvious a method for processing a structure comprising alternating layers of a first silicon-containing material and a silicon-and-germanium-containing material, and wherein the structure comprises a second silicon-containing material overlying and extending into one or more recesses defined by the alternating layers of the first silicon-containing material and the silicon-and-germanium-containing material, wherein multiple steps of contacting the structure with a carbon-containing precursor are performed for replenishing carbon in the silicon-containing materials as recited in the instant claims, in the context of the instant claim.
Regarding claims 12-16, they are dependent on claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIONG-PING LU whose telephone number is (571) 270-1135. The examiner can normally be reached on M-F: 9:00am – 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua L Allen, can be reached at telephone number (571)270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JIONG-PING LU/
Primary Examiner, Art Unit 1713
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