DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 03/24/2026.
Claims 1-20 are pending in this application.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 11/11/2025, and 03/24/2026. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Specification
3. The specification is objected to for the following reason:
The drawings show Fig. 6A, Fig. 6B, Fig. 6C, and the brief description of the drawings at paragraph [0005] combinedly describes as Figures. 1-10.
MPEP 608.01(f) requires a brief description of Fig. 6A, Fig. 6B, Fig. 6C be provided.
Appropriate correction is required.
4. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1-3, 5, 8-11, and 13-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Strong et al. (US 2021/0082825)
Regarding claim 1, Strong discloses a method comprising: forming a composite package substrate 110, shown in Figs. 1, 5-12, comprising:
forming through-openings (in which device-to-device conductive routes 240, and/or conductive vias 178 in Fig. 8 are located) in a dielectric core 160;
filling the through-openings to form a first plurality of through-vias 240, 178 in the dielectric core 160;
forming a first interconnect structure 120 and a second interconnect structure 140 on opposing sides of the dielectric core 160, wherein the first interconnect structure 120 is connected to the second interconnect structure 140 through the first plurality of through-vias 240/178;
bonding a first local interconnect die 180 (1801, 1802) to the first interconnect structure 120;
forming a second plurality of through-vias 344 and/or 342 directly from the first interconnect structure 120;
encapsulating the second plurality of through-vias 344/342 and the first local interconnect die 180 in an encapsulant 190; and
forming a third interconnect structure 310 over and electrically coupling to the first local interconnect die 180 and the second plurality of through-vias 344/342.
Regarding claim 2, Strong discloses the method of claim 1, wherein the forming the second plurality of through-vias 344/342 comprises plating the second plurality of through-vias directly from the first interconnect structure 120. See Figs. 1, 5.
Regarding claim 3, Strong discloses the method of claim 1, wherein the first local interconnect die 180 further comprises a third plurality of through-vias 342 therein, wherein the third plurality of through-vias 342 electrically connect the third interconnect structure 310 to the first interconnect structure 120. See Fig. 1.
Regarding claim 5, Strong discloses the method of claim 1, wherein the dielectric core comprises an organic dielectric material. See para. 0065.
Regarding claim 8, Strong discloses the method of claim 1, further comprising bonding a first package 350 (3501) and a second package 3502 (Fig. 5) to the composite package substrate 110, wherein the first local interconnect die 1801 electrically connect the first package to the second package. See Fig. 5.
Regarding claim 9, Strong discloses the method of claim 8, wherein the first package 350 comprises:
an interposer 360 (Fig. 4); and
a first device die 3301 and a second device die 3302 over and bonding to the interposer 360.
Regarding claim 10, Strong discloses the method of claim 9, wherein the interposer 360 further comprises a second local interconnect die 325, wherein the first device die 3301 is signally connected to the second device die 3302 through the second local interconnect die 325. See Fig. 4.
Regarding claim 11, Strong discloses the method of claim 1, further comprising bonding a first device die 350 (3501) and a second device die 3502 to the composite package substrate 110, wherein the first local interconnect die180 electrically connect the first device die 3501 to the second device die 3502. See Fig. 5, Fig. 27.
Regarding claim 13, Strong discloses a structure comprising: a package substrate (shown in Figs. 1, 5-12) comprising:
a dielectric core 160;
a first plurality of through-vias 240, 178 (Figs. 5, 8, 12) in the dielectric core 160;
a first interconnect structure 120 comprising a first plurality of redistribution lines 136, 138 (Fig. 6) overlying and electrically connected to the first plurality of through-vias 240, 178; and
a second interconnect structure 140 comprising a second plurality of redistribution lines 156, 158 (Fig. 10) underlying and electrically connected to the first plurality of through-vias 240, 178;
a first die 180 (1801, 1802) over and joined to the first interconnect structure 120; and
an encapsulant 190 over and contacting the first interconnect structure 120, wherein the first die 180 is in the encapsulant 190.
Regarding claim 14, Strong discloses the structure of claim 13, wherein the first die 180 comprises a second plurality of through-vias 342 therein, and wherein the second plurality of through-vias 342 are electrically connected to the first plurality of through-vias. See Figs. 1, 5.
Regarding claim 15, Strong discloses the structure of claim 13, further comprising: a first package 350 (3501) and a second package 350 (3502) over and joined to the package substrate 110, wherein the first package is signally connected to the second package through the first die 180. See Fig. 5.
Regarding claim 16, Strong discloses the structure of claim 15, wherein the first package comprises:
an interposer 360 (Fig. 4); and
a first device die 3301 and a second device die 3302 over and joined to the interposer 360.
Regarding claim 17, Strong discloses the structure of claim 16, wherein the interposer 360 further comprises a second die 325, and wherein the first device die is signally connected to the second device die through the second die. See Fig. 4.
Regarding claim 18, Strong discloses a structure comprising: a package substrate (shown in Figs. 1, 5-12) comprising:
a first interconnect structure 120 or 120 & 140 & 160;
a first die 180 (1801, 1802) over and electrically coupling to the first interconnect structure 120; and
a second interconnect structure 310 (Fig. 1) over and electrically coupling to the first interconnect structure 120 and the first die 180; and
an interposer 390 and/or 330 (3301, 3302, Figs. 4-5) over and electrically coupling to the package substrate (via the second interconnect structure 310 and/or the first interconnect structure 120), wherein the interposer is signally coupled to the first die 180, and wherein the interposer further comprises: a second die 3301, 3302.
Regarding claim 19, Strong discloses the structure of claim 18, wherein the first interconnect structure comprises:
a first semiconductor substrate 120-160; and
a first plurality of through-vias 240 136, 138, 156, 158 in the first semiconductor substrate. See Fig. 5-12.
Regarding claim 20, Strong discloses the structure of claim 18, wherein the interposer further comprises a first package component 3801 and a second package component 3802 over the second interconnect structure, wherein the first package component is signally coupled to the second package component through the second interconnect structure. See Fig. 4.
7. Claims 1-7, 12-13, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (US 2022/0045008)
Regarding claim 1, Kang discloses a method comprising: forming a composite package substrate comprising:
forming through-openings CA (Figs. 12-13; and/or through opening in which core conductive patterns 114 are located) in a dielectric core 110;
filling the through-openings (with vias 126 and/or conductive patterns 114) to form a first plurality of through-vias in the dielectric core 110;
forming a first interconnect structure 130 and a second interconnect structure 140 on opposing sides of the dielectric core 110, wherein the first interconnect structure 130 is connected to the second interconnect structure 140 through the first plurality of through-vias;
bonding a first local interconnect die 200/300 to the first interconnect structure 130;
forming a second plurality of through-vias 410 directly from the first interconnect structure 130;
encapsulating the second plurality of through-vias 410 and the first local interconnect die 200/300 in an encapsulant 400; and
forming a third interconnect structure 510 over and electrically coupling to the first local interconnect die 200/300 and the second plurality of through-vias 410.
Regarding claim 2, Kang discloses the method of claim 1, wherein the forming the second plurality of through-vias 410 comprises plating the second plurality of through-vias 410 directly from the first interconnect structure 130. See Fig. 5.
Regarding claim 3, Kang discloses the method of claim 1, wherein the first local interconnect die 200/300 further comprises a third plurality of through-vias therein, wherein the third plurality of through-vias electrically connect the third interconnect structure to the first interconnect structure. See para. 0035.
Regarding claim 4, Kang discloses the method of claim 1, wherein the dielectric core comprises a glass core. See para. 0018.
Regarding claim 5, Kang discloses the method of claim 1, wherein the dielectric core comprises an organic dielectric material. See para. 0018-0019.
Regarding claim 6, Kang discloses the method of claim 1, further comprising:
forming a first additional opening CA in the dielectric core 110; and
embedding a second local interconnect die 120 in the first additional opening CA, wherein the first interconnect structure 130 is connected to the second interconnect structure 140 through additional through-vias 126 in the second local interconnect die 120. See Fig. 5.
Regarding claim 7, Kang discloses the method of claim 1, further comprising:
forming a second additional opening CA in the dielectric core 110; and
embedding a passive device die 120 in the second additional opening CA. See Fig. 5, and paras. 0027-0031. Note that the die 120 of Kang can be any suitable device, such as a local interconnect die recited in claim 6, or a passive device in this claim 7, or any other kind of semiconductor device, depending on the application of the package and/or the choice of the designer.
Regarding claim 12, Kang discloses the method of claim 1, further comprising sawing the composite package substrate from a respective wafer. See para. 0088.
Regarding claim 13, Kang discloses a structure comprising: a package substrate comprising:
a dielectric core 110 (Figs. 12-13);
a first plurality of through-vias CA (Figs. 12-13; and/or through opening in which core conductive patterns 114 are located) in the dielectric core 110;
a first interconnect structure 130 comprising a first plurality of redistribution lines 134 overlying and electrically connected to the first plurality of through-vias; and
a second interconnect structure 140 comprising a second plurality of redistribution lines 144 underlying and electrically connected to the first plurality of through-vias;
a first die 200 or 300 over and joined to the first interconnect structure 130; and
an encapsulant 400 over and contacting the first interconnect structure 130, wherein the first die 200/300 is in the encapsulant 400.
Regarding claim 18, Kang discloses a structure comprising: a package substrate comprising:
a first interconnect structure 140 (Fig. 5);
a first die 120 over and electrically coupling to the first interconnect structure 140; and
a second interconnect structure 130 over and electrically coupling to the first interconnect structure 140 and the first die 120; and
an interposer 400 over and electrically coupling to the package substrate, wherein the interposer 400 is signally coupled to the first die 120, and wherein the interposer 400 further comprises: a second die 200.
Regarding claim 19, Kang discloses the structure of claim 18, wherein the first interconnect structure comprises: a first semiconductor substrate 142; and
a first plurality of through-vias 144 in the first semiconductor substrate. See Fig. 5.
Regarding claim 20, Kang discloses the structure of claim 18, wherein the interposer 400 further comprises a first package component 200 and a second package component 400 over the second interconnect structure 130, wherein the first package component 200 is signally coupled to the second package component 300 through the second interconnect structure 130. See Fig. 5.
8. Claims 1, 2, 4, 6-8, 13, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2023/0187363)
Regarding claim 1, Lin discloses a method comprising: forming a composite package substrate 110 (see Figs. 1, 6, 16) comprising:
forming through-openings (in which conductive pillars 1116 are located) in a dielectric core 1111 (or dielectric core 6114 in Fig. 6);
filling the through-openings to form a first plurality of through-vias 1116 in the dielectric core 1111;
forming a first interconnect structure 1114 and a second interconnect structure 1115 on opposing sides of the dielectric core 1111, wherein the first interconnect structure 1114 is connected to the second interconnect structure 1115 through the first plurality of through-vias 1116;
bonding a first local interconnect die 1133 to the first interconnect structure 1114;
forming a second plurality of through-vias 1131 directly from the first interconnect structure 1114;
encapsulating the second plurality of through-vias 1131 and the first local interconnect die 1133 in an encapsulant 112 and/or 1132; and
forming a third interconnect structure 130 over and electrically coupling to the first local interconnect die 1133 and the second plurality of through-vias 1131. See further Figs. 18-24.
Regarding claim 2, Lin discloses the method of claim 1, wherein the forming the second plurality of through-vias 1131 comprises plating the second plurality of through-vias 1131 directly from the first interconnect structure 130. See Fig. 1.
Regarding claim 4, Lin discloses the method of claim 1, wherein the dielectric core comprises a glass core. See Fig. 13 and para. 0151.
Regarding claim 6, Lin discloses the method of claim 1, further comprising:
forming a first additional opening (in which functional block 601 in Fig. 6 is located) in the dielectric core (Fig. 6: dielectric core 6114, second interconnect structure 1112 on lower side of the dielectric core 6114, and first interconnect structure on upper side of the dielectric core); and
embedding a second local interconnect die 601 in the first additional opening, wherein the first interconnect structure is connected to the second interconnect structure 1112 through additional through-vias in the second local interconnect die.
Regarding claim 7, Lin discloses the method of claim 1, further comprising: forming a second additional opening in the dielectric core; and
embedding a passive device die 601 (see para. 0106) in the second additional opening. See Fig. 6.
Regarding claim 8, Lin discloses the method of claim 1, further comprising bonding a first package 121 and a second package 121 to the composite package substrate, wherein the first local interconnect die 1133 electrically connect the first package to the second package. See Fig. 1.
Regarding claim 13, Lin discloses a structure comprising: a package substrate 110 (Fig. 1) comprising:
a dielectric core 1111;
a first plurality of through-vias 1116 in the dielectric core 1111;
a first interconnect structure 1114 comprising a first plurality of redistribution lines overlying and electrically connected to the first plurality of through-vias 1116; and
a second interconnect structure 1115 comprising a second plurality of redistribution lines underlying and electrically connected to the first plurality of through-vias 1114;
a first die 1133 over and joined to the first interconnect structure 1114; and
an encapsulant 112 and/or 1132 over and contacting the first interconnect structure 1114, wherein the first die 1133 is in the encapsulant 112/1132.
Regarding claim 18, Lin discloses a structure comprising: a package substrate comprising:
a first interconnect structure 1114 or 111 (Fig. 5);
a first die 1133 over and electrically coupling to the first interconnect structure 1114/111; and
a second interconnect structure 130 over and electrically coupling to the first interconnect structure 1114/111 and the first die 1133; and
an interposer 120 over and electrically coupling to the package substrate 110, wherein the interposer 120 is signally coupled to the first die 1133, and wherein the interposer further comprises: a second die 121.
Regarding claim 19, Lin discloses the structure of claim 18, wherein the first interconnect structure 1114/111 comprises: a first semiconductor substrate (para. 0068); and
a first plurality of through-vias 1116 in the first semiconductor substrate. See Fig. 1.
Regarding claim 20, Lin discloses the structure of claim 18, wherein the interposer 120 further comprises a first package component 101 or 121 and a second package component 102 or 121 over the second interconnect structure 130, wherein the first package component is signally coupled to the second package component through the second interconnect structure 130. See Fig. 1.
Claim Rejections - 35 U.S.C. § 103
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 4, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Strong et al. (US 2021/0082825)
Regarding claim 4, Strong discloses the method of claim 1, comprising all claimed limitations, as discussed above, except for wherein the dielectric core comprises a glass core. Strong teaches that the dielectric core 160 can be of organic dielectric material. See para. 0065.
However, it would have been obvious to one of ordinary skills in the art at the time the invention was made that a dielectric core can obviously be of organic dielectric materials (as recited in instant claim 5) or of glass material (recited in claim 4). These are well known dielectric materials for a dielectric core. It would have been obvious to one of ordinary skills in the art at the time the invention was made that selecting a known material on the basis of its suitability for the intended use is just within the general skill of a worker in the art.
MPEP § 2144.07 states that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (Claims to a printing ink comprising a solvent having the vapor pressure characteristics of butyl carbitol so that the ink would not dry at room temperature but would dry quickly upon heating were held invalid over a reference teaching a printing ink made with a different solvent that was nonvolatile at room temperature but highly volatile when heated in view of an article which taught the desired boiling point and vapor pressure characteristics of a solvent for printing inks and a catalog teaching the boiling point and vapor pressure characteristics of butyl carbitol; “Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle.” 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of aknown plastic to make a container of a type made of plastics prior to the invention washeld to be obvious); Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323(Fed. Cir. 1988) (Claimed agricultural bagging machine, which differed from a prior art machine only in that the brake means were hydraulically operated rather than mechanically operated, was held to be obvious over the prior art machine in view of references which disclosed hydraulic brakes for performing the same function, albeit in a different environment.).
Caterpillar Inc. v. Deere & Co., 224 F.3d 1374, 56USPQ2d 1305 (Fed. Cir. 2000); Al-Site Corp. v. VSI Int ’ l, Inc., 174 F.3d 1308, 1316, 50 USPQ2d 1161, 1165 (Fed. Cir. 1999); Chiuminatta Concrete Concepts, Inc. v. Cardinal Indus. Inc., 145 F.3d 1303, 1309, 46 USPQ2d 1752, 1757 (Fed. Cir. 1998); Lockheed Aircraft Corp. v. United States , 193 USPQ 449, 461 (Ct. Cl. 1977 ); Data Line Corp. v. Micro Technologies, Inc., 813 F.2d 1196, 1 USPQ2d 2052 (Fed. Cir. 1987). In re Leshin, 125 USPQ 416.
See also MPEP § 2183.
Regarding claim 12, Strong discloses the method of claim 1 comprising all claimed limitations, as discussed above., except for further comprising sawing the composite package substrate from a respective wafer.
However, it would have been obvious to one of ordinary skills in the art at the time the invention was made that the composite package substrate can be multiply formed from a single wafer, then singling or dicing the wafer to form a plurality of individual composite package substrates by sawing the wafer, for the benefit of cost reducing cost.
Conclusion
11. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 September 23, 2026
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