DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 08 July 2026 have been fully considered but they are not persuasive.
Contrary to the remarks please consider the following:
a/ “Yoo does not disclose a “serial data buffer”.
Yoo may not have explicitly said his disclosure is directed to a “serial data buffer”. Nonetheless, the “serial data buffer” is merely a name of the “arrangement” with all the features believed to be disclosed by Yoo. The “serial data buffer” in the pre-ample without further relation to the body of the claim was NOT given patentable weight. In fact, it could have been labeled as “A device” and would not have made any difference. In other words, if the so called “serial data buffer” is defined or limited by the body/features of the claim, anything that meets the limitations or the features of the body of the claim is considered to BE the so-called “serial data buffer”.
b/ “Yoo also does not disclose a “controller-side output port to output the read data to the memory controller”.
It should be noted that applicant does not argue against the “controller-side INPUT port”. An admission of the claimed “INPUT PORT” side should be an inherent/implicit expression/implication of “OUTPUT” port. If input exists in electronic circuitry. Output is INHERENT.
First, it should be noted that the fig. 3 is the details of the page remapper 150 shown in fig. 2. And the fig. 2 is the bad page managing unit 110 of fig. 1. Fig. 1 has the memory controller 100 and the memory device 200. Paragraph 0098 of Yoo discloses “the decoder 120 decodes an address included in the REQUEST”. IN fig. 2, the request comes from the host from the input-side of the decoder 120, also shown in fig. 1 from the HOST side of the memory controller 100.
In the claim, which is contrary to the remarks, the memory command is received from the input port of the memory controller. While para 0100 discloses “a command and an address that are needed to access the DRAM 200 are generated by the scheduling unit 140. One should realize that the generated command and address is merely decoded signal from the host request. The scheduling unit 140 does not DECIDE the command and address. The command and address are within/part of the request from the HOST, as common sense in the memory art.
Next, the decoded/recognizable command and address are then sent to 200 through Bust B1. Paragraph 0093 – 0103 disclose how the system redirects the requested bad page to the remapped spare page for consistent memory operation.
In para 0101, “When the remapping address is output from the bus B1 of the scheduling unit 140, A SPARE PAGE IS ACCESSED INSTEAD OF A BAD PAGE”. This is considered Yoo’s teaching for “Yoo does not disclose a “controller-side output port to output the read data to the memory controller”. “A spare page is accessed instead of a bad page” technically means the read data from the spare page is output as read data to the memory controller.
In conclusion, while Yoo et al. did not clearly disclose the apparatus (so-called arrangement in the remarks) to be called as a Serial Data Buffer, this is again only mentioned in the pre-amble which was not given patentable weight. Further, since all the limitations are considered met by the prior disclosure in Yoo et al., the Office believe that this apparatus by Yoo may be used as Serial Data Buffer if intended to.
And since all the required limitations in the claims “language” are considered met, the rejection is therefore maintained as follow (per claims mapping).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 2, 3, 5, 13, 14, 16 and 21 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Yoo et al. (US Pat pub 2015/0067248).
Regarding claims 2, 13, and 21, Yoo et al. disclose a serial data buffer (for example figs. 1 – 16 and all related texts) comprising:
a controller-side input port to receive a memory command including an input address from a memory controller (host request side of unit 110, figs. 1 and 2);
mapping logic to apply a function to the input address to generate a remapped address (see para 0009, 0093. See also para 0017, 0018, 0025, 0033 – 0035, 0039, etc…, hidden function to receive bad page information and to remap bad ages of the DRAM);
a memory-side output port to output the memory command including the remapped address to a memory device (see para 0161, “memory controller controls the scheduler 142 to provide a command and a remapping address output”);
a memory-side input port to receive read data from the memory device when the memory command comprises a read command (para 0053, commands of a DRAM such as … “read”. Para 0156 discloses “read operation” … sensing amplifier sensing data stored in memory cells, as a result of read operation. See also para 0176 and 0178); and
a controller-side output port to output the read data to the memory controller (para 0012, referred to as bus B2 from memory device 200 to controller 100, fig. 1 and 2. See also para 0080).
Regarding claims 3 and 14, Yoo et al. also disclose the serial data buffer of claim 2 and 13, wherein the mapping logic modifies at least one of a chip identifier, a bank group, a bank address, a row address, or a column address of the input address (see para 0029, “an address generator receiving an input address to generate an internal address for an address remapping”).
Regarding claims 5 and 16, Yoo et al. also disclose the serial data buffer of claim 2 and 13, further comprising a register to store a parameter value affecting the function applied to the input address to generate the remapped address (referred to as the register file, para 0016, 0038, 0106, etc…).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (US Pat Pub 2015/0067248) in view of Calabro et al. (EP 3 496 277 A1).
Regarding claims 4 and 15, Yoo et al. disclose the serial data buffer of claim 2, except
wherein the mapping logic comprises a circular shift register to apply a circular shift to the input address to generate the remapped address.
This feature is however taught by Calabro et al. (see page 9, para 0118, “linear count may be REMAPPED to the actual RAM addresses contained in the look-up table and generated from the CIRCULAR SHIFT factors …”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to combine the features taught by the prior arts as cited, so that VLSI implementation may be simplified (see page 10, para 0121).
Allowable Subject Matter
Claims 6 – 12 and 17 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
See additional cited references for related disclosures to the claimed invention.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm.
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LY D. PHAM
Examiner
Art Unit 2827
/LY D PHAM/Primary Examiner, Art Unit 2827 August 11, 2026
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