Prosecution Insights
Last updated: October 02, 2026
Application No. 18/895,205

SEMICONDUCTOR PACKAGE STRUCTURE

Non-Final OA §103
Filed
Sep 24, 2024
Priority
Feb 25, 2021 — continuation of 12/100,697
Examiner
FERNANDES, ERROL V
Art Unit
Tech Center
Assignee
Advanced Semiconductor Engineering Inc.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
701 granted / 821 resolved
+25.4% vs TC avg
Moderate +11% lift
Without
With
+10.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
26 currently pending
Career history
830
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
62.3%
+22.3% vs TC avg
§102
33.3%
-6.7% vs TC avg
§112
4.0%
-36.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 821 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 5-7, 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ding et al. US 2017/0254968 A1 in view of Lu et al. US 2021/0134751 A1. Regarding claim 1, Ding discloses: A semiconductor package structure (Fig. 3), comprising: an electronic device (Fig. 3 in view of Fig. 5A FOWLP); and a photonic device (130) disposed over the electronic device, wherein the photonic device has a first sidewall (right) and a second sidewall (left) opposite to the first sidewall, the first sidewall defines a space configured to connect to an optical component (138) and the second sidewall overlaps the electronic device in the cross-sectional view perspective. Ding does not disclose: the first sidewall does not overlap the electronic device in a cross-sectional view perspective. Lu discloses a publication from a similar field of endeavor in which: A photonic device (30) where the first sidewall (right) does not overlap the electronic device (20, 60,50) in a cross-sectional view perspective and the second sidewall (left) overlaps the electronic device in the cross-sectional view perspective (Fig. 3). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to extending the first sidewall of Ding the such that it does not overlap the electronic device to further define an alternative configuration as shown by Lu at least to allow further stability to the overall optical assembly and desired configuration options for particular applications. (claim 5) Lu: an electronic device (20); a first and second pillar (50). (claim 6) Lu: a conductive element (40). (claim 7) Lu: an encapsulant (60). (claim 9) Ding: a first conductive bump (136); a second conductive bump (119 under 136); and a third conductive bump (119). Claims 2-4, 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ding/Lu, as applied to claim 1, in view of Tseng et al. US 2021/0193605 A1. Regarding claims 2-4, Ding/Lu do not disclose: (claim 2) further comprising a redistribution layer disposed between the electronic device and the photonic device, wherein a sidewall of the redistribution layer overlaps the photonic device in the cross-sectional view perspective; (claim 3) further comprising: a first conductive bump and a second conductive bump electrically connecting the redistribution layer to the photonic device; and a non-conductive layer between the first conductive bump and the second conductive bump; and (claim 4) wherein the non-conductive layer contacts the photonic device and the redistribution layer. Tseng discloses a publication from a similar field of endeavor in which: a redistribution layer (152) disposed over an electronic device (130); and a first conductive bump (172) and a second conductive bump (172) electrically connected to the redistribution layer for external connections (Fig. 15). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the redistribution layer of Tseng disposed between the electronic device and the photonic device of Ding/Lu such that a sidewall of the redistribution layer overlaps the photonic device in the cross-sectional view perspective and connected through the conductive bumps in order to allow desired routing of the electrical connections. Furthermore, although Tseng does not disclose “a non-conductive layer between the first conductive bump and the second conductive bump” such that “[it] contacts the photonic device and the redistribution layer” in the combination with Ding/Lu, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to understand that such material would be known in the art to protect the bump connections from physical damage/environment and add mechanical stability to the overall assembly. Regarding claim 8, Ding/Lu do not disclose: further comprising a redistribution layer contacting the encapsulant and electrically connected to the first conductive pillar, the second conductive pillar, and the conductive element. Tseng discloses a publication from a similar field of endeavor in which: further comprising a redistribution layer (152) contacting the encapsulant (140) and electrically connected to the first conductive pillar (120), the second conductive pillar (120), and the conductive element (135) (Fig. 15). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the redistribution layer of Tseng contacting the similar encapsulant and electrically contacting the similar first/second conductive pillars and conductive element of Ding/Lu to allow desired routing of the electrical connections between the electronic device and photonic device. Claims 10-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ding et al. US 2017/0254968 A1 in view of Tseng et al. US 2021/0193605 A1. Regarding claims 10-14, Ding discloses: A semiconductor package structure (Fig. 3), comprising: a photonic device (130) comprising a recess structure (recess 130 where 138 fits) configured to accommodate an optical component (138); and an electronic device (Fig. 3 in view of Fig. 5A FOWLP) disposed under the photonic device. Ding does not disclose: wherein the electronic device comprises a substrate and a first conductive via passing through the substrate, the first conducive via comprises a first conductive layer, and at least a portion of the first conductive layer extends over a bottom surface of the substrate. Tseng discloses a publication from a similar field of endeavor in which: wherein the electronic device (120, 130, 140) comprises a substrate (110b and/or 140) and a first conductive via (120) passing through the substrate, the first conducive via comprises a first conductive layer (180/870), and at least a portion of the first conductive layer extends over a bottom surface of the substrate (Fig. 15). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the similar conductive via structures of Tseng within the assembly of Ding to electrically connect the electronic device to the photonic device to provide a more stable structure. (claims 11-13) Tseng: Fig. 15; showing second conductive via (120). (claim 14) Tseng: first/second UBM (180b); and solder element (870). Regarding claims 15-20, Ding discloses: A semiconductor package structure (Fig. 3), comprising: a photonic device (130) comprising a recess structure (recess 130 where 138 fits) configured to accommodate an optical component (138); and an electronic device (Fig. 3 in view of Fig. 5A FOWLP) disposed under the photonic device. Ding does not disclose: wherein the electronic device comprises a substrate and a first conductive via passing through the substrate and electrically connected to the photonic device; and a redistribution layer disposed between the photonic device and the substrate, wherein the redistribution layer is electrically connected to the first conductive via and the photonic device. Tseng discloses a publication from a similar field of endeavor in which: wherein the electronic device (120, 130, 140) comprises a substrate (110b and/or 140) and a first conductive via (120) passing through the substrate; and a redistribution layer (152) is electrically connected to the first conductive via (Fig. 15). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the similar conductive via structures and redistribution layer of Tseng within the assembly of Ding to electrically connect the electronic device to the photonic device providing a more stable structure while also allowing desired routing of the electrical connections. (claims 16-18) Tseng: Fig. 15; showing second conductive via (120); first/second UBM (180b); and solder element (870). (claims 19 and 20) Tseng: Fig. 15; first and second conductive traces (154a-154c) relative to the first/second UBMs (180b). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERROL V FERNANDES/Primary Examiner, AU 2893
Read full office action

Prosecution Timeline

Sep 24, 2024
Application Filed
Sep 23, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
96%
With Interview (+10.8%)
2y 2m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 821 resolved cases by this examiner. Grant probability derived from career allowance rate.

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