Prosecution Insights
Last updated: October 02, 2026
Application No. 18/901,953

PSEUDO-SUBSTRATE WITH IMPROVED EFFICIENCY OF USAGE OF SINGLE CRYSTAL MATERIAL

Final Rejection §103§112
Filed
Sep 30, 2024
Priority
Sep 04, 2012 — FR 1258227 +4 more
Examiner
CAILLOUET, CHRISTOPHER C
Art Unit
1745
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Soitec
OA Round
2 (Final)
68%
Grant Probability
Favorable
3-4
OA Rounds
12m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
518 granted / 765 resolved
+2.7% vs TC avg
Moderate +15% lift
Without
With
+14.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 12m
Avg Prosecution
26 currently pending
Career history
786
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
54.7%
+14.7% vs TC avg
§102
15.0%
-25.0% vs TC avg
§112
22.7%
-17.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 765 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim Rejections - 35 USC § 112 The amendment of claim 19 has rendered the 112(b) rejection of the previous office action moot. Claim Rejections - 35 USC § 103 Claim(s) 1-3 and 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa et al. (US 20120021588) in view of Iwamoto (US 20110278993) and Deguet et al. (US 20090246933). As to claim 1, Hasegawa discloses a method of manufacturing SOI substrate and semiconductor device (Abstract). Hasegawa discloses that the method comprises of: providing a single crystal substrate 110 comprising a piezoelectric material; providing an oxide layer 114 on a surface of the single crystal substrate; bonding a handle substrate 100 to the oxide layer on a side opposite the single crystal substrate; and separating a layer of the piezoelectric material of the single crystal substrate adjacent the oxide layer from a remainder of the single crystal substrate to provide the pseudo-substrate comprising the layer of the piezoelectric material, the handle substrate, and the oxide layer therebetween (Fig. 1A, 1B, 1C, 1D, 1E, 1F; ¶56-69; 92). Hasegawa discloses that the crystal substrate may be thinned to a desired thickness (Id.). Hasegawa fails to specifically teach or disclose whether the quartz may be replaced with lithium tantalate or lithium niobate. Both Iwamoto (¶6) and Deguet (¶58) disclose that quartz, lithium tantalate and lithium niobate are known interchangeable piezoelectric materials. It would have been obvious to modify the method of Hasegawa and replace the quartz with lithium tantalate or lithium niobate because both Iwamoto and Deguet teach that they are known functional piezoelectric equivalents. As to claim 2, the method of claim 1 is taught as seen above. Hasegawa discloses that the piezoelectric layer may have a thickness of 10-500 microns which encompasses the recited thickness range (Id.). As to claim 3, the method of claim 1 is taught as seen above. Hasegawa discloses that the handle substrate 100 may comprise of silicon (Id.). As to claims 5 and 7, the method of claim 1 is taught as seen above. Hasegawa discloses that the oxide layer may comprise of silicon oxide by chemical vapor deposition (¶69). As to claim 6, the method of claim 1 is taught as seen above. Hasegawa does not disclose any polishing steps prior to the application of the oxide layer. Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al. (US 20120086312) in view of Letertre (US 20040187766), JP 2010135605 (hereinafter JP '605) and Hasegawa et al. (US 20120021588). As to claim 21, Kobayashi discloses a method of making composite substrate (Abstract) comprising: providing a piezoelectric layer 11 which is bonded to a final substrate 12, wherein the piezoelectric layer has a thickness of 10-50 microns (Fig. 2; ¶25). Kobayashi discloses that the piezoelectric crystal lithium tantalate (paragraph 25). Kobayashi discloses that the piezoelectric crystal layer of lithium tantalite having a diameter of 10 cm and a thickness of 250 microns is cut and bonded to a silicon carrier wafer to form a pseudo-substrate, followed by thinning to a thickness of 40 microns (paragraphs 25 and 42-47), but fails to specifically teach or disclose how the piezoelectric layer is procured for bonding to the final substrate. Letertre discloses a method of manufacturing wafer slices by making a perpendicular cut into the cylindrical crystal ingot (24) to form a disk-shaped slice of wafer material that has the same cross-sectional area as the single crystal ingot (Fig. 6 below). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the ingot cutting method of Letertre in the method taught by Kobayashi because one of ordinary skill in the art would have been able to carry out such a substitution to achieve the predictable result of providing a known and conventional method of providing disk shaped wafers for placement upon a substrate. “The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.” KSR Int’l Co. v. Teleflex Inc., 127 S.Ct. 1727, 82 USPQ2d 1385 (2007). Furthermore, it would have been obvious to modify the method of the above references as combined with a known and conventional ingot cutting method, such as cutting method which produces disc shaped wafers from an ingot disclosed by Letertre, because such a modification would have been within his technical grasp. PNG media_image1.png 517 507 media_image1.png Greyscale The above references as combined fail to specifically teach or disclose if a handle substrate is utilized to support the crystal piece after cutting from the ingot. JP ‘605 discloses a method of manufacturing pseudo-substrate by: providing a single crystal ingot (9); providing a handle substrate (91); cutting a thin slice (9a) from the ingot and attaching said slice to said handle substrate with an adhesive (92) to form a pseudo-substrate (Fig. 1 and 2). It would have been obvious to one of ordinary skill in the art at the time of filing to use the handling method of JP ‘605 in the method taught by the above references as combined because one of ordinary skill in the art would have been able to carry out such a substitution to achieve the predictable result of providing a known conventional and successful method of handling a thin piece of crystal material upon cutting from an ingot for further processing of said crystal material. “The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.” KSR Int’l Co. v. Teleflex Inc., 127 S.Ct. 1727, 82 USPQ2d 1385 (2007). The above references fail to specifically teach or disclose that the crystal substrate of the assembly is thinned. Hasegawa discloses a method of manufacturing SOI substrate and semiconductor device (Abstract). Hasegawa discloses that it is known and conventional in the art to thin a crystal layer to a desired thickness after it is separated and bonded to a substrate (¶92). It would have been obvious to one of ordinary skill in the art at the time of filing to use the crystal thinning method of Hasegawa in the method taught by the above references as combined because one of ordinary skill in the art would have been able to carry out such a substitution to achieve the predictable result of providing a known conventional and successful means for thinning a crystal layer to a desired thickness in a piezoelectric component manufacturing process. “The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.” KSR Int’l Co. v. Teleflex Inc., 127 S.Ct. 1727, 82 USPQ2d 1385 (2007). Double Patenting The terminal disclaimer filed on July 7, 2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of U.S. Patent No 10,910,256 has been reviewed and is accepted. The terminal disclaimer has been recorded. Allowable Subject Matter Claims 8-20 are allowed. The following is an examiner’s statement of reasons for allowance: Claim 8 recites a method for fabricating a structure, comprising: preparing a first pseudo-substrate, including: providing a single crystal substrate comprising a piezoelectric material; forming an oxide layer on a surface of the single crystal substrate; and transferring a piezoelectric layer of the single crystal substrate adjacent the oxide layer to a handle substrate to form the first pseudo-substrate comprising the piezoelectric layer of the single crystal substrate having a first surface and a second surface opposite the first surface, the oxide layer adjacent the first surface of the piezoelectric layer of the single crystal substrate, and the handle substrate adjacent the oxide layer; in-depth weakening the first pseudo-substrate by ion implantation at a certain depth in the first pseudo-substrate; bonding the first pseudo-substrate to a substrate to provide an assembly comprising the piezoelectric layer of the single crystal substrate, the oxide layer adjacent the first surface of the piezoelectric layer of the single crystal substrate, the handle substrate adjacent the oxide layer, and the substrate adjacent the second surface of the piezoelectric layer of the single crystal substrate; and separating the assembly at the ion-implanted depth of the first pseudo-substrate to form: the structure comprising at least a portion of the piezoelectric layer of the single crystal substrate on the substrate, and a second pseudo-substrate comprising a remainder portion of the piezoelectric layer of the single crystal substrate, the oxide layer adjacent the surface of the remainder portion of the piezoelectric layer, and the handle substrate adjacent the oxide layer. None of the prior art teaches or discloses a method of fabricating a piezoelectric structure with the recited steps of ion implantation to weaken the first pseudo-substrate at a certain depth to separate the handle from the pseudo-substrate as currently claimed. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments Applicant's arguments filed July 7, 2026 have been fully considered but they are not persuasive. Examiner will address only those arguments pertinent to the rejection above. Applicant argues on pages 11 and 12 that none of the prior art, and specifically Hasegawa as modified by Iwamoto fails to make obvious using lithium tantalate and lithium niobate in place of quartz as the piezoelectric material. Applicant argues that Hasegawa fails to teach or disclose that the aim of the invention is to achieve piezoelectric properties and therefore one of ordinary skill would not have found any motivation to choose a piezoelectric material. This argument is not persuasive because the claim does not recite that the method is directed for the production of a piezoelectric product, just a pseudo-substrate with a piezoelectric material. As seen in the rejection above, quartz is a piezoelectric material and lithium tantalate and lithium niobate are known functional equivalents. As to claim 21, the method of the references as combined does not include an in-depth weakening of the single crystal substrate by ion implantation and splitting the single crystal substrate of the assembly at a weakening location. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. eAny inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER C CAILLOUET whose telephone number is (571)270-3968. The examiner can normally be reached M-F 9AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PHILLIP TUCKER can be reached at (571)272-1095. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER C CAILLOUET/Examiner, Art Unit 1745 /GEORGE R KOCH/Primary Examiner, Art Unit 1745
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Prosecution Timeline

Sep 30, 2024
Application Filed
Mar 24, 2026
Non-Final Rejection mailed — §103, §112
Jul 07, 2026
Response Filed
Sep 23, 2026
Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
68%
Grant Probability
82%
With Interview (+14.8%)
2y 12m (~12m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 765 resolved cases by this examiner. Grant probability derived from career allowance rate.

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