DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/7/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-6, 8-10, 12-13, 16-20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Denesh (US 20180114878 A1)
Regarding claim 1, Denesh discloses (Fig. 41) A light emitting element comprising: a first semiconductor layer (804) doped with a first conductivity type (n, ¶ [0369]); a stress relief layer (1120) disposed on the first semiconductor layer, the stress relief layer comprising an indium-containing layer (1122, ¶ [0371]) containing a nitride-based semiconductor material containing indium (1122), and doped with the first conductivity type (n, ¶ [0369]); a light emitting layer (1130) disposed on the stress relief layer, the light emitting layer comprising a quantum well layer (1132, 1133, ¶ [0396], Fig. 42) containing a nitride-based semiconductor material containing indium (1132) in a composition greater than or equal to an indium composition of the indium-containing layer (¶ [0385] discloses indium content of the quantum well 1132 in a range from 0.26-0.55; ¶ [0372] discloses indium content of indium-containing layer 1122 in a range from 0.08 to 0.12); and a second semiconductor layer (1150) disposed on the light emitting layer and doped with a second conductivity type (p, ¶ [0390]), wherein the indium composition of the indium-containing layer is in a range of about 30% to about 100% of an indium composition of the quantum well layer (¶ [0372] discloses indium content of the indium-containing layer 1122 in a range from 0.08-0.12, ¶ [0385] discloses the quantum well layer 1132 in a range from 0.26 to 0.55, as such it would make the indium content of the indium-containing layer to be about 0.3 to 1 of the indium content of the quantum well).
Regarding claim 2, Danesh discloses the light emitting element of claim 1, wherein a doping concentration of the indium-containing layer is about 1x1016/cm3 or more (¶ [0388 discloses intrinsic layer 1120 has a free charge carrier not greater than 1x1016/cm3 as such the n-type structure 1120 (¶ [0375]) would have a doping concentration of about 1x1016/cm3 or more).
Regarding claim 4, Danesh discloses the light emitting element of claim 1, wherein a thickness of the indium-containing layer (1122) is about 2 nm or more (¶ [0374]).
Regarding claim 5, Danesh discloses The light emitting element of claim 1, further comprising (Fig. 42, ¶ [0371]): a superlattice layer (1110) disposed between the first semiconductor layer and the stress relief layer, wherein the superlattice layer is formed as multiple layers in which a first layer containing a nitride-based semiconductor material containing indium (1112) and a second layer containing a nitride-based semiconductor material that does not contain indium (1114) are alternately disposed.
Regarding claim 6, Danesh discloses the light emitting element of claim 5, wherein an Indium composition of the superlattice layer (1112) is less than about 30% of the indium composition of the quantum well layer (¶ [0372] discloses indium content of 1112 in a range from 4-8%; ¶ [0385] discloses indium content of 1132 in a range from 26-55%, making the former is less than 30% of the latter).
Regarding claim 8, Danesh discloses the light emitting element of claim 5, further comprising (Fig. 42): a spacer layer (1118) disposed between the superlattice layer and the stress relief layer, the spacer layer containing a nitride-based semiconductor material that does not contain indium, wherein a thickness of the spacer layer is about 20 nm or more (¶ [0383]).
Regarding claim 9, Danesh discloses the light emitting element of claim 1, wherein (Fig. 42) the quantum well layer (1132) contains InGaN (¶ [0370]), and the indium-containing layer (1122) contains InGaN or InAlGaN (¶ [0371]).
Regarding claim 10, Danesh discloses the light emitting element of claim 1, wherein the indium-containing layer directly contacts the light emitting layer (Fig. 42).
Regarding claim 12, Danesh discloses the light emitting element of claim 1, wherein (Fig. 42, ¶ [0371]) the stress relief layer (1120) is formed as multiple layers in which a plurality of indium-containing layers comprising the indium-containing layer (1122) and a plurality of intermediate layers containing a nitride-based semiconductor material that does not contain indium (1124) are alternately disposed.
Regarding claim 13, Danesh discloses the light emitting element of claim 12, wherein an indium composition of the plurality of indium-containing layers (1122) gradually changes from the indium-containing layer at a lower portion adjacent to the first semiconductor layer to the indium-containing layer at an upper portion adjacent to the light emitting layer (¶ [0382]).
Regarding claim 16, Danesh discloses the light emitting element of claim 1, wherein an indium fluctuation in the light emitting layer is at least about 10% higher than an indium fluctuation in the stress relief layer (¶¶ [0372, 0385], 4-8% 26-55%).
Regarding claim 17, Danesh discloses the light emitting element of claim 1, wherein (Fig. 42, ¶ [0385]) the indium composition of the quantum well layer (1132) is about 25% or more (26-55%), and an emission wavelength of the light emitting layer is in a range of about 500 nm to about 750 nm (¶ [0370]).
Regarding claim 18, Danesh discloses (Fig. 40B) A display device (¶ [0009]) comprising: a pixel (10B, 10G, 10R) comprising a first pixel electrode (796, ¶ [0359]), a second pixel electrode (804, ¶ [0359], Fig. 41), and a light emitting element (10R, 10B, 10G) electrically connected between the first pixel electrode and the second pixel electrode, wherein the light emitting element comprises (Fig. 42): a first semiconductor layer (804) doped with a first conductivity type (n, ¶ [0369]); a stress relief layer (1120) disposed on the first semiconductor layer, the stress relief layer comprising an indium-containing layer (1122, ¶ [0371]) containing a nitride-based semiconductor material containing indium (1122), and doped with the first conductivity type (¶ [0370]); a light emitting layer (1130) disposed on the stress relief layer , the light emitting layer comprising a quantum well layer (1132, 1133, ¶ [0396], Fig. 42) containing a nitride-based semiconductor material containing indium (1132); and a second semiconductor layer (1150, ¶ [0390]) disposed on the light emitting layer and doped with a second conductivity type (p), and an indium composition of the indium-containing layer is in a range of about 30% to about 100% of an indium composition of the indium (¶ [0372] discloses indium content of the indium-containing layer 1122 in a range from 0.08-0.12, ¶ [0385] discloses the quantum well layer 1132 in a range from 0.26 to 0.55, as such it would make the indium content of the indium-containing layer to be about 0.3 to 1 of the indium content of the quantum well).
Regarding claim 19, Danesh discloses the display device of claim 18, wherein a doping concentration of the indium-containing layer is about 1x1016/cm3 or more (¶ [0388 discloses intrinsic layer 1120 has a free charge carrier not greater than 1x1016/cm3 as such the n-type structure 1120 (¶ [0375]) would have a doping concentration of about 1x1016/cm3 or more).
Regarding claim 20, Danesh discloses the display device of claim 18, wherein (Fig. 42) the light emitting element further comprises a superlattice layer (1110) disposed between the first semiconductor layer (804) and the stress relief layer (1120), and the superlattice layer contains a nitride-based semiconductor material containing indium (1112) in a composition less than about 30% of the indium composition of the quantum well layer (¶ [0372] discloses indium content of the indium-containing layer 1112 in a range from 0.04-0.08, ¶ [0385] discloses the quantum well layer 1132 in a range from 0.26 to 0.55, as such it would make the indium content of the indium-containing layer to be less than 0.3 of the indium content of the quantum well).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 7, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Denesh (US 20180114878 A1)
Regarding claim 3, Danesh discloses the light emitting element of claim 1. Danesh is silent regarding a doping concentration of the indium-containing layer is lower than a doping concentration of the first semiconductor layer. Artisans in the art would have appreciated that in semiconductor device fabrication, the stress relief layer is often thin, lightly doped or intrinsic layer placed between the substrate and the active region because a heavily doped layer would create a large concentration of free carrier, which can shunt current and reduce the effective electric field in the active region. By keeping the stress relief layer lightly doped, high resistivity is maintained, allowing the semiconductor’s intrinsic properties to dominate in the active area. As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to dope the indium-containing layer of the stress relief layer with a lighter doping concentration than the first semiconductor layer to optimize applications.
Regarding claim 7, Danesh discloses the light emitting element of claim 5. Danesh is silent wherein a doping concentration of the indium-containing layer (1122) is lower than a doping concentration of the first semiconductor layer (804). Artisans in the art would have appreciated that in semiconductor device fabrication, the stress relief layer is often thin, lightly doped or intrinsic layer placed between the substrate and the active region because a heavily doped layer would create a large concentration of free carrier, which can shunt current and reduce the effective electric field in the active region. By keeping the stress relief layer lightly doped, high resistivity is maintained, allowing the semiconductor’s intrinsic properties to dominate in the active area. As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to dope the indium-containing layer of the stress relief layer with a lighter doping concentration than the first semiconductor layer to optimize applications.
Regarding claim 11, Danesh discloses the light emitting element of claim 1. Danesh discloses the stress relief layer is a superlattice layer comprising alternating layers 1122 and 1124 (Fig. 42). Danesh in another embodiment, Fig. 36, discloses the stress relief layer is a single layer (808) formed of the indium-containing layer, and an indium composition of the stress relief layer gradually changes from a lower portion adjacent to the first semiconductor layer to an upper portion adjacent to the light emitting layer (¶ [0341] disclosing indium content of 808 as a graded composition increasing from 804 to 808). As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the stress relief layer of Danesh (Fig. 36) for the stress relief layer of Danesh (Fig. 42) without changing the function of the light emitting device. Doing so would allow for a diversity of applications.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being anticipated by Denesh (US 20180114878 A1) in view of Shen (US 20030085409 A1)
Regarding claim 14, Danesh discloses the light emitting element of claim 1. Danesh is silent regarding wherein a doping concentration of the stress relief layer gradually changes from a lower portion adjacent to the first semiconductor layer to an upper portion adjacent to the light emitting layer.
Shen discloses (Fig. 3) a light emitting device comprising a first semiconductor layer (204), a stress relief layer (206), a light emitting layer (208) and a second semiconductor layer (214), wherein the stress relief layer (206) has a graded dopant concentration (¶ [0027]).
Artisans in the art would have appreciated that in light emitting device fabrication, a graded dopant concentration layer in a stress relief layer can improve performance by addressing multiple interrelated challenges such as improved charge injection and transport, allowing certain regions to facilitate hole or electron injection while maintaining balanced transport in others. e.g. in red OLEDs, a higher dopant concentration near the charge generation layer can enhance hole mobility while a lower concentration in other regions helps maintain color stability at low current. As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the stress relief layer of Danesh with a graded dopant concentration stress relief layer of Shen for optimal applications.
Regarding claim 15, Danesh in view of Shen discloses the light emitting element of claim 14. Danesh fails to disclose wherein the doping concentration of the stress relief layer gradually decreases from a lower portion adjacent to the first semiconductor layer to an upper portion adjacent to the light emitting layer. Artisans in the art would have appreciated that in semiconductor device fabrication, the stress relief layer is often thin, lightly doped or intrinsic layer placed between the substrate and the active region because a heavily doped layer would create a large concentration of free carrier, which can shunt current and reduce the effective electric field in the active region. By keeping the stress relief layer lightly doped at the portion closer to the active layer, high resistivity is maintained, allowing the semiconductor’s intrinsic properties to dominate in the active area. As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to dope the stress relief layer with a graded dopant concentration higher at the portion close to the semiconductor layer and lower at the portion closer to the light emitting layer.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Okuno (US 20130161586 A1) and Chakraborty (US 7769066 B2) disclose a light emitting device with indium-containing nitride-based stress relief layer.
Conclusion
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/DTH/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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