SEMICONDUCTOR DEVICES WITH LENGTH-GRADED CHANNEL

§102 §103 §112

DETAILED ACTION Claims 1–40 are pending and have been examined on the merits below. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Domestic Benefit This application does not claim the benefit of any prior-filed application under 35 U.S.C. 119(e), 120, 121, 365(c), or 386(c). Applicant’s Application Data Sheet filed 09 October 2024 does not identify a parent application. See MPEP § 211 et seq. Foreign Priority This application does not claim foreign priority under 35 U.S.C. 119(a)–(d) or 365(b). The Application Data Sheet filed 09 October 2024 leaves the Foreign Priority Information section blank. No certified copy is required. Information Disclosure Statement No information disclosure statement under 37 CFR 1.97 is of record. Should Applicant file an IDS, it will be considered if timely under 37 CFR 1.97 and 1.98. Specification The title of the invention is not descriptive. 37 CFR 1.72(a); MPEP § 606.01. Independent claims 1, 11, and 33 do not require a length-graded channel. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title or similar is suggested: Vertical Semiconductor Device Having a Sidewall Gate Region and a Sidewall Channel Region The specification uses “channel layer” and “channel region” interchangeably for the same epitaxial layer (compare [0039] “n-type channel region 50” with claim 1 “channel layer”). Applicant may pick one term and use it throughout. No substitute specification is required at this time if Applicant elects to leave the specification as filed and rely on the claims. Claim 5 recites “the sidewall channel layer.” The specification and claim 1 use “sidewall channel region.” The same slip appears in claim 31. See the 112(b) rejection below. Correction of the claims will suffice. Claim Interpretation The claims are given their broadest reasonable interpretation consistent with the specification. MPEP § 2111. The specification is used to understand the meaning of claim terms, not to import unrecited embodiment details into the claims. Claim 1 does not require silicon carbide, a JFET label, a graded doping profile, or any particular implant angle. Claim 21 does not require a sidewall gate region. Claim 33 does not require two implant angles. Claim Rejections - 35 USC 112 The following is a quotation of 35 U.S.C. 112(b): The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 5 and 31 are rejected under 35 U.S.C. 112(b) as being indefinite. Antecedent basis. Claim 5 depends from claim 1 and recites “the sidewall channel layer.” Claim 1 introduces a “sidewall channel region” and a “channel layer,” not a sidewall channel layer. Claim 31 depends from claim 30, which depends from claim 28, which depends from independent claim 27. Claim 27 introduces a “sidewall channel region,” and that region is what claims 28 and 30 carry forward. Claim 31 recites “the sidewall channel layer.” In each case there is no antecedent basis for “the sidewall channel layer.” Applicant may overcome the rejection by amending “sidewall channel layer” to “sidewall channel region” in claims 5 and 31. Claim Rejections - 35 USC 102 and 103 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless — (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. The following is a quotation of 35 U.S.C. 103: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized after MPEP § 2141. The Office further notes that this application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. A. Prior Art Rejections Based on Primary Reference Bhalla ’215 Bhalla et al., U.S. Patent No. 10,396,215 B2 (issued 27 August 2019; filed 09 September 2016) (“Bhalla ’215”). Bhalla ’215 is prior art under 35 U.S.C. 102(a)(1). Claims 1, 5, 11, 14, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bhalla ’215. Regarding independent claim 1, Bhalla ’215 teaches a vertical semiconductor device (FIG. 2; Abstract; col. 5, ll. 15–45), comprising a drift layer (240) doped with dopants of a first conductivity type (col. 5, ll. 20–35); a mesa on the drift layer (the raised stripe between adjacent trenches; col. 5, ll. 20–40), and a trench adjacent to the mesa (etched through the source and the channel core into the drift; col. 5, ll. 25–40), wherein the mesa comprises a mesa sidewall (the wall of the mesa that faces the trench; FIG. 2), the mesa comprising a channel layer (lightly doped channel core 230; Abstract; col. 5, ll. 30–55) and a source layer (201) on the channel layer (FIG. 2), wherein the channel layer is between the source layer and the drift layer (201, then 230, then 240; FIG. 2); a sidewall gate region (p-type regions 202) in the mesa adjacent the mesa sidewall (vertical and angled implants 203; FIG. 2; FIG. 3; col. 5, ll. 35–55), the sidewall gate region doped with dopants of a second conductivity type that is different from the first conductivity type (opposite the n-type source, channel, and drift; col. 5); and a sidewall channel region (205) in the channel layer adjacent the sidewall gate region (behind the vertical gate segments; Abstract; FIG. 2; FIG. 4; col. 5, ll. 45–67), the sidewall channel region doped with dopants of the first conductivity type (n-type angled implant 204; col. 5, l. 55 through col. 6, l. 15) and having a second doping concentration that is greater than the first doping concentration (peak of 205 about 4×10¹⁷ to 4×10¹⁸ cm⁻³, about 10–100× the core; col. 6; Abstract); wherein the channel layer is doped with dopants of the first conductivity type and has a first doping concentration (230 is first-type at about 1×10¹⁵ cm⁻³; col. 6); and wherein the sidewall gate region extends deeper toward the drift layer than the sidewall channel region (col. 6: the channel-implant depth is close to the gate depth, slightly shallower or deeper; the slightly shallower alternative places gate 202 deeper toward drift 240 than channel 205; see FIG. 2, exemplary cell: drift 240, channel core 230, source 201, sidewall gate 202, angled sidewall channel 205). PNG media_image1.png 2050 1466 media_image1.png Greyscale FIG. 2 of Bhalla ’215 Regarding claim 5, Bhalla ’215 teaches the channel layer (230) has a first length in a vertical direction (the thickness of 230 from source 201 down to drift 240; FIG. 2) and the sidewall channel region (205) has a second length in the vertical direction that is less than the first length (col. 6: the channel implant may be slightly shallower than the gate, so 205 does not occupy the full vertical span of 230). Regarding independent claim 11, Bhalla ’215 teaches a method of forming a vertical semiconductor device (FIGS. 3–4; col. 5–6) comprising forming a mesa in a semiconductor layer and a trench adjacent to the mesa, the mesa comprising a mesa sidewall, a channel layer (230) and a source layer (201) on the channel layer, the semiconductor layer, the channel layer and the source layer having a first conductivity type (n-type stack; FIG. 2); implanting second conductivity type dopant ions into a sidewall of the mesa at a first implant angle (gate implant 203 at angle α, with hard mask 310 in place; FIG. 3) to form a sidewall gate region (202) in the mesa; and implanting first conductivity type dopant ions into the sidewall of the mesa at a second implant angle (channel implant 204 at angle β; FIG. 4) to form a sidewall channel region (205) in the channel layer adjacent to the sidewall gate region, wherein the first implant angle is different from the second implant angle (in at least one embodiment of Bhalla ’215, the mask is removed and the channel implant is applied at a larger angle β than the gate implant α, and that larger angle places the charge pockets deeper; FIG. 4). PNG media_image2.png 2008 874 media_image2.png Greyscale FIG. 4 of Bhalla ’215 Regarding claims 14 and 15, Bhalla ’215 teaches the channel layer (230) extends deeper in the mesa than the sidewall channel region (205; claim 14) and the sidewall gate region (202) extends deeper toward the drift layer than the sidewall channel region (claim 15; in at least one embodiment of Bhalla ’215, the channel implant is slightly shallower than the gate, so 205 stops short of the bottom of 230 and gate 202 extends past 205 toward the drift; col. 6). Bhalla et al., U.S. Patent No. 10,446,695 B1 (issued 15 October 2019) (“Bhalla ’695”). Bhalla ’695 is prior art under 35 U.S.C. 102(a)(1). Claims 2–4, 13, 16–18, 21–32, 36, and 38–40 are rejected under 35 U.S.C. 103 as being unpatentable over Bhalla ’215 in view of Bhalla ’695. Regarding claims 2–4, 16–18, 22–24, 28–30, and 38–40, Bhalla ’215 teaches the sidewall channel region (205) adjacent the sidewall gate region (202; the angled implant, its energy, and shadowing set where that dose sits along the sidewall; FIGS. 3–4; col. 5–6). Bhalla ’215 does not in so many words call that profile step-graded (claims 2, 16, 22, 28, and 38) or continuously graded (claims 4, 18, 24, 30, and 40), or a higher concentration in an upper portion nearer the source and a lower concentration toward the drift (claims 3, 17, 23, 29, and 39). Bhalla ’695, is directed to the same trench vertical JFET and states the problem with that cell: precise control of threshold voltage is difficult because threshold voltage varies with the amount and the position of charge in the channel. Bhalla ’695 then solves that problem by further implants that vary the doping inside the channel, including a vertical channel made of more than one layer of different doping concentration. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to grade the sidewall channel region (205) of Bhalla ’215, higher nearer the source and lower toward the drift, for the reason Bhalla ’695 gives (put the charge where it sets threshold, instead of leaving a uniform sidewall dose whose position is not controlled). Regarding claims 13, 21–24, 27–31, and 36, Bhalla ’215 has the sidewall channel region (205) beside the sidewall gate region (202) (the implant beam does not reach the bottom of the sidewall when the mesa and trench geometry shadows it; col. 5, angle α is chosen from trench depth, mask thickness, and trench width; the result is more implanted dose in an upper portion of the sidewall, nearer the source, and less dose in a lower portion, nearer the drift). Bhalla ’695 supplies the reason to use that profile on purpose rather than design it out. Bhalla ’695 states that threshold voltage of a trench vertical JFET varies with the amount and the position of charge in the channel, and solves it by changing the doping along the channel. One of ordinary skill in the art before the effective filing date of the claimed invention would therefore keep the source-high, drift-low sidewall dose that Bhalla ’215’s own angled implant produces, because Bhalla ’695 identifies that position of charge as what has to be set. The same reason applies where the sidewall channel region has a second doping concentration that is greater than the first doping concentration of the drift layer (claim 27; Bhalla ’215 already dopes 205 well above drift 240, about 1×10¹⁷ cm⁻³ and up, against a drift of about 1×10¹⁶ cm⁻³ or 1×10¹⁵ cm⁻³; col. 6). Regarding claims 25, 26, and 32, claim 25 and claim 26 depend from claim 21, and claim 32 depends from claim 27. The sidewall channel region has a second length in the vertical direction that is less than the length of the channel layer (claim 25; col. 6, the slightly shallower channel-implant alternative), and the sidewall gate region extends deeper toward the drift layer than the sidewall channel region (claims 26 and 32; the same slightly shallower alternative; col. 6). The graded sidewall channel of claim 21, and the sidewall-channel concentration greater than the drift concentration of claim 27, are obvious over Bhalla ’215 in view of Bhalla ’695 for the reasons above. Claims 6–10, 12, 19, 20, 33–35, and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Bhalla ’215. Regarding claims 6, 7, 8, 9, 10, and 20, the first doping concentration (claim 6), the second doping concentration (claim 7), the mesa width (claim 8), the trench width (claim 9), the aspect ratio of trench depth to mesa width (claim 10), and a mesa width less than the trench width (claim 20; Bhalla ’215 adjusts mesa width, trench depth, and the doping ratio of sidewall channel 205 to channel core 230 to set threshold and to keep the lightly doped core from dominating the charge; same order of magnitude, mesa about 0.3–2 μm, peak of 205 about 1×10¹⁷ to 4×10¹⁸ cm⁻³, core 230 about 1×10¹⁵ cm⁻³; col. 6) appear to be a result-effective variable1 that may be optimized2 given the general conditions of the claim. Regarding claims 12 and 19, the first implant angle is greater than the second implant angle (claim 12; in at least one embodiment of Bhalla ’215 the mask is removed and β may be larger than α, and which angle is larger is a result-effective choice tied to whether hard mask 310 is still present and whether shadowing is wanted or avoided; FIG. 4; col. 5–6)1,2, and one angle is less than 30 degrees and the other is greater than 30 degrees (claim 19; the same choice of α and β; col. 5–6). Regarding independent claim 33, Bhalla ’215 teaches forming a plurality of mesas (repeating cell; FIG. 2) in a semiconductor layer and a trench adjacent to each mesa, each mesa comprising a channel layer (230) and a source layer (201) on the channel layer, the channel layer and the source layer having a first conductivity type (n-type; FIG. 2); and implanting first conductivity type dopant ions into a sidewall of each mesa (angled implant 204; FIG. 4; col. 5–6) to form a sidewall channel region (205) in the channel layer of each mesa. A second mesa has a width different from a first mesa (the ordinary spread of trench width, mesa width, mask thickness, and angle, which is what Bhalla ’215 uses to decide whether the implant is shadowed; col. 5), so the implant lands at a different depth (a sidewall channel may stop short of the full depth of the channel layer, the slightly shallower alternative; col. 6), due to a process variation (claim 33’s name for that width difference). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that two mesas of different width, formed in the same process, end up with sidewall channel regions at two different depths. Regarding claims 34, 35, and 37, each depends from claim 33. The second implant angle is less than the first implant angle (claim 34; after hard mask 310 is removed, Bhalla ’215 allows channel-implant angle β to be larger than gate-implant angle α, and the reverse pairing is the same choice; FIGS. 3–4; col. 5–6). The sidewall channel regions extend less than the full depth of the channel layer (claim 35; col. 6, the slightly shallower channel-implant alternative), and the sidewall gate region extends deeper toward the drift layer than the sidewall channel region (claim 37; the same slightly shallower alternative; col. 6). B. Prior Art Rejections Based on Primary Reference Odekirk ’410 Odekirk et al., U.S. Patent No. 8,519,410 B1 (issued 27 August 2013) (“Odekirk ’410”). Odekirk ’410 is prior art under 35 U.S.C. 102(a)(1). Claims 1, 11, 12, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Odekirk ’410 in view of Bhalla ’215. Regarding independent claim 1, Odekirk ’410 teaches a vertical semiconductor device (SiC vertical-sidewall static induction transistor; Abstract; FIG. 6) comprising a drift layer (102), a mesa on the drift layer and a trench adjacent to the mesa (channel mesa 114; FIG. 6), a source layer on the mesa, and a sidewall gate region (gate junctions 122a) in the mesa adjacent the mesa sidewall (angled acceptor implant 103; FIG. 6), the sidewall gate region doped with dopants of a second conductivity type. Odekirk ’410 does not teach a sidewall channel region of the first conductivity type having a second doping concentration greater than a first doping concentration of the channel layer, with the sidewall gate region extending deeper toward the drift layer than that sidewall channel region (Bhalla ’215 forms sidewall channel 205 by angled implant 204, doped well above core 230, and in at least one embodiment the channel implant is slightly shallower than the gate so the gate extends deeper toward the drift; col. 5–6; FIGS. 2–4; Abstract). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to put Bhalla ’215’s angled first-type sidewall channel, doped above the channel layer and stopped short of the gate depth, onto the mesa of Odekirk ’410. The reason is the one Bhalla ’215 gives for doing it: the epitaxial charge between the sidewall gates does not set threshold tightly enough, and the angled channel implant does. Regarding independent claim 11 and claims 12 and 14, Odekirk ’410 implants the sidewall gate at an acute angle (FIG. 6a). Odekirk ’410 does not teach a second implant angle different from the first implant angle that forms a sidewall channel region of the first conductivity type (Bhalla ’215: gate implant at angle α with hard mask 310 in place, and in at least one embodiment the mask is removed and the channel implant is applied at a larger angle β, different from α, which places the charge pockets deeper; FIGS. 3–4; col. 5–6). The channel layer extending deeper in the mesa than the sidewall channel region (claim 14; the slightly shallower channel implant; col. 6), and the first implant angle being greater than the second implant angle (claim 12; which angle is larger is the same choice; col. 5–6). Allowable Subject Matter None as written. In at least one embodiment of Bhalla ’215, the mask is removed and the channel implant is applied at a larger, deeper angle, which anticipates claim 11. Claims 12 and 19 are the further choice of which angle is larger, and they are obvious over Bhalla ’215 for the optimization stated above. The grade limitations are obvious over Bhalla ’215 in view of Bhalla ’695 for the reason Bhalla ’695 states. A rewrite of claim 1 that actually required both (i) a sidewall gate extending into the drift and (ii) a source-high, drift-low sidewall channel used to desensitize DIBL to mesa-width variation would be a different question. The present independent claims do not require that combination. Double Patenting No double-patenting rejection is made at this time. The Application Data Sheet identifies no parent. The Office reserves the right to consider nonstatutory double patenting against other Wolfspeed / Cree cases in the same family of trench JFET cells if a continuing relationship is later claimed or if a conflict is identified. Conclusion A shortened statutory period for reply to this non-final action is set to expire THREE MONTHS from the mailing date of this communication. Extensions of time may be available under 37 CFR 1.136(a). In no event, however, may a reply be timely filed after SIX MONTHS from the mailing date of this communication. Claims 1–40 are rejected. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P DULKA whose telephone number is (571)270-7398. The examiner can normally be reached Monday-Friday, 9am-5pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ELISEO RAMOS-FELICIANO can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. 24 September 2026 /John P. Dulka/Primary Examiner, Art Unit 2817 1 In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977) (A particular parameter must first be recognized as a result-effective variable before determination of the optimum or workable ranges of said variable might be characterized as routine experimentation). 2 In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation). See MPEP § 2144.05(II).