DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claim Objections
Claims 21-27 are objected to because of the following informalities:
The term “a first CA interface” in claim 21, line 9 should be “a first command-and-address (CA) interface”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 26 and 27 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The recitation of “wherein the voltage signal encodes at least a portion of the configuration information.” In claim 26 and the recitation of “wherein the value encodes at least a portion of the configuration information.” in claim 27 are not disclosed in the specification or shown in any of the drawings.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21 and 22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 9 of U.S. Patent No. 9,117,496. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 21 and 22 are anticipated by claims 1 and 9 of the patent.
Regarding claim 21, claims 1 and 9 of the patent recites a memory controller, comprising:
a first circuit to send a memory access command to a set of memory devices (it is inherent that there is a controller used to send a memory access command to the set of memory devices); and
a second circuit to provide configuration information to the set of memory devices (claim 9, at least two memory devices), wherein the configuration information specifies an operational mode in which the set of memory devices is to be operated, and wherein the operational mode is selected from a set of operational modes (claim 1, line 5);
wherein the set of operational modes includes a first operational mode (claim 1, a second operational mode) in which a first CA interface of a first memory device (claim 1 and claim 9, a first memory device in the at least two memory devices) in the set of memory devices is active, a second CA interface of the first memory device in the set of memory devices is inactive, a third CA interface of a second memory device (the second memory device in the at least two memory devices) in the set of memory devices is inactive, and a fourth CA interface of the second memory device in the set of memory devices is active, and wherein the first memory device and the second memory device are disposed in a clamshell configuration such that the first CA interface is substantially aligned with third CA interface and the second CA interface is substantially aligned with the fourth CA interface (claim 9); and
wherein the set of operational modes includes a second operational mode (claim 1, a first operational mode) in which both CA interfaces of a single memory device (one of the at least two memory devices) in the set of memory devices are active.
Regarding claim 22, it is inherent that the memory device has a third circuit (data line connected to a write driver) to receive data from at least one data interface of at least one memory device.
Claim 23 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 9 of U.S. Patent No. 9,117,496 n view of Maule et al. (US 2010/0162020, hereinafter “Maule”).
Claim 23 differs from claims1 and 9 of US Patent No. 9,117,496 in reciting that the configuration information specifies at least a width of at least one data interface of at least one memory device. However, Maule discloses a specific data width of the memory interface is required to reduce loading and permit higher transfer rates (paragraph [0022]). It would have been obvious to one having ordinary skill in the art to have configuration information that specifies at least a width of at least one data interface of at least one memory device to reduce loading and permit higher transfer rates
Allowable Subject Matter
Claims 28-40 are allowed.
Claims 24-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 24, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the set of operational modes includes a third operational mode in which a first data interface of at least one memory device is active and a second data interface of the at least one memory device is inactive.” in combination with the other limitations thereof as is recited in the claim. Claim 25 depends on claim 24.
Regarding claim 28, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “a circuit to output configuration information, wherein: based on first configuration information, each of the first and second CA interfaces provides respective first and second memory access commands to corresponding first and second memory device interfaces disposed on a single DRAM device; and based on second configuration information: the first CA interface provides first memory access commands to the first memory device interface disposed on a first DRAM device; and the second CA interface provides second memory access commands to the second memory device interface disposed on a second DRAM device.” in combination with the other limitations thereof as is recited in the claim. Claims 29-35 depend on claim 28.
Regarding claim 36, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “outputting, by the IC, configuration information, wherein: based on first configuration information, each of the first and second CA interfaces provides respective first and second memory access commands to corresponding first and second memory device interfaces disposed on a single DRAM device; and based on second configuration information: the first CA interface provides first memory access commands to the first memory device interface disposed on a first DRAM device; and the second CA interface provides second memory access commands to the second memory device interface disposed on a second DRAM device.” in combination with the other limitations thereof as is recited in the claim. Claims 37-40 depend on claim 36.
Conclusion
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/HUAN HOANG/Primary Examiner, Art Unit 2827
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