DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/11/2024 and 06/24/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US PG Pub 2021/0005638 to Noh et al (hereinafter Noh).
Regarding Claim 1, Noh discloses a semiconductor element comprising:
a semiconductor layer (Fig. 11, 310);
an insulating film (114) disposed on the semiconductor layer;
an electrode (330) disposed on the insulating film; and
a surface protective film (115) covering the semiconductor layer, the insulating film, and the electrode,
wherein the electrode includes:
a first barrier layer (331) to prevent Al from diffusing into the insulating film;
a metal layer (332) formed on the first barrier layer and made of Al or an alloy mainly composed of Al [0043]; and
a second barrier layer (333) formed on the metal layer to protect the metal layer, and
wherein a side surface of the metal layer is disposed inside a side surface of the first barrier layer and inside a side surface of the second barrier layer (Fig. 11).
Regarding Claim 4, Noh discloses the semiconductor element according to Claim 1, wherein:
the semiconductor element has an insulating gate structure (114);
the insulating film includes a gate insulating film (114, [0033]); and
the electrode includes a gate electrode (330).
Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US PG Pub 2019/0131322 to Ito et al (hereinafter Ito).
Regarding Claim 1, Ito discloses a semiconductor element comprising:
a semiconductor layer (Fig. 6B, 202);
an insulating film (206) disposed on the semiconductor layer;
an electrode (201) disposed on the insulating film; and
a surface protective film (205) covering the semiconductor layer, the insulating film, and the electrode,
wherein the electrode includes:
a first barrier layer to prevent Al from diffusing into the insulating film [0019];
a metal layer formed on the first barrier layer and made of Al or an alloy mainly composed of Al [0019]; and
a second barrier layer formed on the metal layer to protect the metal layer [0019], and
wherein a side surface of the metal layer is disposed inside a side surface of the first barrier layer and inside a side surface of the second barrier layer (Fig. 6B).
Regarding Claim 3, Ito discloses the semiconductor element according to Claim 1, wherein a void (V201) is formed between the side surface of the metal layer and the surface protective film.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Noh as applied to Claim 1 above and in further view of US PG Pub 2016/0071732 to Nishii et al (hereinafter Nishii).
Regarding Claim 5, Noh discloses the semiconductor element according to Claim 1 but does not disclose the gate electrode in a trench within the semiconductor layer.
Nishii discloses a semiconductor layer with a trench (Fig. 11; 730/740) and includes a gate insulating film (750) continuously disposed over a bottom surface of the trench, a side surface of the trench, and a vicinity of the trench of a surface of the semiconductor layer (Fig. 11) and a gate electrode (860) continuously disposed over the bottom surface of the trench, the side surface of the trench, and the vicinity of the trench of the surface of the semiconductor layer through the insulating film.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the gate structure of Noh to comprise a trench gate. Trench gates were known in the art to provide benefits such as greater control over the channel region and/or lengthening channel regions without increasing the overall size of the transistor.
Allowable Subject Matter
Claims 6-12 are allowed.
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 6 recites a method for manufacturing a semiconductor element comprising:
forming an insulating film on a semiconductor layer;
forming an electrode by depositing a first barrier layer to prevent Al from diffusing into the insulating film, a metal layer made of Al or an alloy mainly composed of Al, and a second barrier layer to protect the metal layer in this order on the insulating film;
etching including dry etching the electrode in a direction perpendicular to a main surface of the semiconductor layer to form a predetermined pattern, and dry etching a side surface of the metal layer so that the side surface of the metal layer is disposed inside a side surface of the first barrier layer and inside a side surface of the second barrier layer; and
forming a surface protective film to cover the semiconductor layer and the electrode.
While the references of record disclose a similar structure to that claimed by Applicant, the references do not arrive at the structures using the method claimed by Applicant. Noh utilizes a wet etching process (Noh [0042]) and Ito creates a void by way of a heat treatment process (Ito, [0013]). A search of other, relevant references does not show Applicant’s invention to be anticipated or obvious. Claims 7-12 depend on Claim 6 and are allowable for at least the reasons above.
Claim 2 requires the side surface of the metal layer be covered with an oxide film made of aluminum oxide. The references do not disclose an aluminum oxide formed on the surface of the metal layer and Applicant notes that the oxidation of the metal helps further prevent aluminum diffusion. A search of other, relevant references does not show Applicant’s invention to be anticipated or obvious.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
