DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites that “the first insulating layer and the second insulating layer expose the buffer layer in an area not overlapping all of the semiconductor layer, the first conductive patterns and the second conductive pattern.” “All of here can mean two separate things: that the area does not overlap all of these layers (does not overlap at least one), or that it does not overlap any of these layers. As set forth in In re Miyazaki, “if a claim is amenable to two or more plausible claim constructions, the USPTO is justified in requiring the applicant to more precisely define the metes and bounds of the claimed invention by holding the claim unpatentable under 35 U.S.C. §112, second paragraph, as indefinite.” 89 USPQ2d 1207, 1211 (Bd. Pat. App. & Int. 2008).
Claim 3 recites that an area in which the second insulating layer is not disposed is filled with the planarization layer in the area in which the first conductive patterns do not overlap the second conductive pattern. This appears to recite two different areas that the area in which the planarization layer is filled, which is confusing.
Claim 4 is rejected based on its dependency.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Park, US 2019/0267440 A1.
Claim 1: Park discloses
a substrate (110);
a semiconductor layer (A1) which is disposed on the substrate;
a first insulating layer 112) which is disposed on the semiconductor layer;
first conductive patterns (G1) which are disposed on the first insulating layer;
a second insulating layer (113) which is disposed on the first conductive patterns;
and a second conductive pattern (C2) which is disposed on the second insulating layer,
wherein the second insulating layer is disposed in an area overlapping at least any one of the semiconductor layer and the second conductive pattern (both, FIG. 12) and is not disposed in an area in which the first conductive patterns and the second conductive pattern do not overlap.
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Claim 2: Park discloses a buffer layer (111) which is disposed between the substrate and the semiconductor layer, wherein the first insulating layer and the second insulating layer expose the buffer layer in an area not overlapping all of the semiconductor layer, the first conductive patterns and the second conductive pattern (FIG. 13).
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Claim 3: Park discloses a planarization layer (161) which is disposed on the second conductive pattern, wherein an area in which the second insulating layer (113) is not disposed is filled with the planarization layer in the area in which the first conductive patterns do not overlap the second conductive pattern.
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Claim 4 would potentially distinguish over the prior art if the 112 rejection above is addressed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and is listed in the attached Notice of References Cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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